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| author | Thomas Munro <tmunro@postgresql.org> | 2022-03-18 13:40:26 +1300 |
|---|---|---|
| committer | Thomas Munro <tmunro@postgresql.org> | 2022-03-18 13:40:26 +1300 |
| commit | b2397aae23982b77de29d3a55b263a03852d0714 (patch) | |
| tree | 5fc67311614ef2aecdd88f9f52155d9d350e14d2 /src | |
| parent | d7b5c071dd6af2b81a7042dc60295061c7230cdc (diff) | |
| download | postgresql-b2397aae23982b77de29d3a55b263a03852d0714.tar.gz postgresql-b2397aae23982b77de29d3a55b263a03852d0714.zip | |
Declare aarch64 has single copy atomicity for 8 byte values.
Architecture Reference Manual for ARMv8 B2.2.1 [1]
For explicit memory effects generated from an Exception level the
following rules apply:
- A read that is generated by a load instruction that loads a single
general-purpose register and is aligned to the size of the read in the
instruction is single-copy atomic.
- A write that is generated by a store instruction that stores a single
general-purpose register and is aligned to the size of the write in the
instruction is single-copy atomic.
[1] https://documentation-service.arm.com/static/61fbe8f4fa8173727a1b734e
https://developer.arm.com/documentation/ddi0487/latest
Author: Yura Sokolov <y.sokolov@postgrespro.ru>
Reviewed-by: Thomas Munro <thomas.munro@gmail.com>
Reviewed-by: Alexander Korotkov <aekorotkov@gmail.com>
Discussion: https://postgr.es/m/f7f3f0febe27862711f924a7b0f39e065e547f4b.camel%40postgrespro.ru
Discussion: https://postgr.es/m/CA%2BhUKGKyJf7kwYkqDgzTE26Ra1m9nvM%3Deds2RSSu7WSL-r2wKw%40mail.gmail.com
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/port/atomics/arch-arm.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/include/port/atomics/arch-arm.h b/src/include/port/atomics/arch-arm.h index 2083e3230db..9fe8f1b95f7 100644 --- a/src/include/port/atomics/arch-arm.h +++ b/src/include/port/atomics/arch-arm.h @@ -23,4 +23,10 @@ */ #if !defined(__aarch64__) && !defined(__aarch64) #define PG_DISABLE_64_BIT_ATOMICS +#else +/* + * Architecture Reference Manual for ARMv8 states aligned read/write to/from + * general purpose register is atomic. + */ +#define PG_HAVE_8BYTE_SINGLE_COPY_ATOMICITY #endif /* __aarch64__ || __aarch64 */ |