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| author | Tom Lane <tgl@sss.pgh.pa.us> | 2022-04-06 18:57:57 -0400 |
|---|---|---|
| committer | Tom Lane <tgl@sss.pgh.pa.us> | 2022-04-06 18:58:14 -0400 |
| commit | a82a5eee314df52f3183cedc0ecbcac7369243b1 (patch) | |
| tree | 66b56e90a4483c68930a083534fc1963859464a7 /src | |
| parent | 8ea7963fc741b6f403a544d56ad0ecf78e5237b1 (diff) | |
| download | postgresql-a82a5eee314df52f3183cedc0ecbcac7369243b1.tar.gz postgresql-a82a5eee314df52f3183cedc0ecbcac7369243b1.zip | |
Use ISB as a spin-delay instruction on ARM64.
This seems beneficial on high-core-count machines, and not harmful
on lesser hardware. However, older ARM32 gear doesn't have this
instruction, so restrict the patch to ARM64.
Geoffrey Blake
Discussion: https://postgr.es/m/78338F29-9D7F-4DC8-BD71-E9674CE71425@amazon.com
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/storage/s_lock.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h index 8a5a905e380..af1145d98f6 100644 --- a/src/include/storage/s_lock.h +++ b/src/include/storage/s_lock.h @@ -337,6 +337,23 @@ tas(volatile slock_t *lock) #define S_UNLOCK(lock) __sync_lock_release(lock) +/* + * Using an ISB instruction to delay in spinlock loops appears beneficial on + * high-core-count ARM64 processors. It seems mostly a wash for smaller gear, + * and ISB doesn't exist at all on pre-v7 ARM chips. + */ +#if defined(__aarch64__) || defined(__aarch64) + +#define SPIN_DELAY() spin_delay() + +static __inline__ void +spin_delay(void) +{ + __asm__ __volatile__( + " isb; \n"); +} + +#endif /* __aarch64__ || __aarch64 */ #endif /* HAVE_GCC__SYNC_INT32_TAS */ #endif /* __arm__ || __arm || __aarch64__ || __aarch64 */ |