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| author | John Naylor <john.naylor@postgresql.org> | 2022-08-25 13:37:40 +0700 |
|---|---|---|
| committer | John Naylor <john.naylor@postgresql.org> | 2022-08-25 13:37:40 +0700 |
| commit | 4112e39f70eed8d699ea5be7f5945a8970023d0d (patch) | |
| tree | f37f5ab8bbdb02f79e65666d3c912ee88b9731c5 /src | |
| parent | b4ddf3ee30bfb5b7da60411cabcf0589bdbd3f42 (diff) | |
| download | postgresql-4112e39f70eed8d699ea5be7f5945a8970023d0d.tar.gz postgresql-4112e39f70eed8d699ea5be7f5945a8970023d0d.zip | |
Remove unused symbol __aarch64
This was added as a possible variant of __aarch64__ back when 64-bit
ARM was vaporware. It hasn't shown up in the wild since then, so remove.
Nathan Bossart
Discussion: https://www.postgresql.org/message-id/CAFBsxsEN5nW3uRh%3Djrs-QexDrC1btu0ZfriD3FFfb%3D3J6tAngg%40mail.gmail.com
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/port/atomics.h | 3 | ||||
| -rw-r--r-- | src/include/port/atomics/arch-arm.h | 4 | ||||
| -rw-r--r-- | src/include/storage/s_lock.h | 8 |
3 files changed, 7 insertions, 8 deletions
diff --git a/src/include/port/atomics.h b/src/include/port/atomics.h index f7cd0f6f20c..b14ce832bf8 100644 --- a/src/include/port/atomics.h +++ b/src/include/port/atomics.h @@ -63,8 +63,7 @@ * compiler barrier. * */ -#if defined(__arm__) || defined(__arm) || \ - defined(__aarch64__) || defined(__aarch64) +#if defined(__arm__) || defined(__arm) || defined(__aarch64__) #include "port/atomics/arch-arm.h" #elif defined(__i386__) || defined(__i386) || defined(__x86_64__) #include "port/atomics/arch-x86.h" diff --git a/src/include/port/atomics/arch-arm.h b/src/include/port/atomics/arch-arm.h index 9fe8f1b95f7..7449f8404a0 100644 --- a/src/include/port/atomics/arch-arm.h +++ b/src/include/port/atomics/arch-arm.h @@ -21,7 +21,7 @@ * 64 bit atomics on ARM32 are implemented using kernel fallbacks and thus * might be slow, so disable entirely. On ARM64 that problem doesn't exist. */ -#if !defined(__aarch64__) && !defined(__aarch64) +#if !defined(__aarch64__) #define PG_DISABLE_64_BIT_ATOMICS #else /* @@ -29,4 +29,4 @@ * general purpose register is atomic. */ #define PG_HAVE_8BYTE_SINGLE_COPY_ATOMICITY -#endif /* __aarch64__ || __aarch64 */ +#endif /* __aarch64__ */ diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h index cc83d561b29..65aa66c5984 100644 --- a/src/include/storage/s_lock.h +++ b/src/include/storage/s_lock.h @@ -256,7 +256,7 @@ spin_delay(void) * We use the int-width variant of the builtin because it works on more chips * than other widths. */ -#if defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(__aarch64) +#if defined(__arm__) || defined(__arm) || defined(__aarch64__) #ifdef HAVE_GCC__SYNC_INT32_TAS #define HAS_TEST_AND_SET @@ -277,7 +277,7 @@ tas(volatile slock_t *lock) * high-core-count ARM64 processors. It seems mostly a wash for smaller gear, * and ISB doesn't exist at all on pre-v7 ARM chips. */ -#if defined(__aarch64__) || defined(__aarch64) +#if defined(__aarch64__) #define SPIN_DELAY() spin_delay() @@ -288,9 +288,9 @@ spin_delay(void) " isb; \n"); } -#endif /* __aarch64__ || __aarch64 */ +#endif /* __aarch64__ */ #endif /* HAVE_GCC__SYNC_INT32_TAS */ -#endif /* __arm__ || __arm || __aarch64__ || __aarch64 */ +#endif /* __arm__ || __arm || __aarch64__ */ /* |