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| author | Igor Sysoev <igor@sysoev.ru> | 2008-01-29 07:06:18 +0000 |
|---|---|---|
| committer | Igor Sysoev <igor@sysoev.ru> | 2008-01-29 07:06:18 +0000 |
| commit | 48b7b9bd0e6ee241ec5f6317c2ce60eb1d30607d (patch) | |
| tree | 70db50c4ed789cbd7d508822e1810a7e1a6a7fee /src/core/ngx_cpuinfo.c | |
| parent | 442d1e63f267c5cb4ef9ed6f2b11158af33da68e (diff) | |
| download | nginx-48b7b9bd0e6ee241ec5f6317c2ce60eb1d30607d.tar.gz nginx-48b7b9bd0e6ee241ec5f6317c2ce60eb1d30607d.zip | |
detect L2 cache line size for Intel Core
Diffstat (limited to 'src/core/ngx_cpuinfo.c')
| -rw-r--r-- | src/core/ngx_cpuinfo.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/core/ngx_cpuinfo.c b/src/core/ngx_cpuinfo.c index 587f97811..68eb094c9 100644 --- a/src/core/ngx_cpuinfo.c +++ b/src/core/ngx_cpuinfo.c @@ -96,9 +96,18 @@ ngx_cpuinfo(void) /* Pentium */ case 5: + ngx_cacheline_size = 32; + break; + /* Pentium Pro, II, III */ case 6: ngx_cacheline_size = 32; + + if ((cpu[0] & 0xf0) >= 0xd0) { + /* Intel Core */ + ngx_cacheline_size = 64; + } + break; /* |