import {AssemblyInstructionInfo} from '../base.js'; export function getAsmOpcode(opcode: string | undefined): AssemblyInstructionInfo | undefined { if (!opcode) return; switch (opcode.toUpperCase()) { case "ADD": return { "html": "

ADD rd, rs1, rs2

ADD performs the addition of rs1 and rs2. SUB performs the subtraction of rs2 from rs1. Overflows are ignored and the low XLEN bits of results are written to the destination rd. SLT and SLTU perform signed and unsigned compares respectively, writing 1 to rd if rs1 < rs2, 0 otherwise. Note, SLTU rd, x0, rs2 sets rd to 1 if rs2 is not equal to zero, otherwise sets rd to zero (assembler pseudoinstruction SNEZ rd, rs). AND, OR, and XOR perform bitwise logical operations.

ISA: rv32

", "tooltip": "ADD performs the addition of rs1 and rs2. SUB performs the subtraction of rs2 from rs1. Overflows are ignored and the low XLEN bits of results are written to the destination rd. SLT and SLTU perform signed and unsigned compares respectively, writing 1 to rd if rs1 < rs2, 0 otherwise. Note, SLTU rd, x0, rs2 sets rd to 1 if rs2 is not equal to zero, otherwise sets rd to zero (assembler pseudoinstruction SNEZ rd, rs). AND, OR, and XOR perform bitwise logical operations.\n\n\n\n(ISA: rv32)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#integer-register-register-operations" }; case "ADD.UW": return { "html": "

ADD.UW rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "ADDI": return { "html": "

ADDI rd, rs1, imm12

ADDI adds the sign-extended 12-bit immediate to register rs1. Arithmetic overflow is ignored and the result is simply the low XLEN bits of the result. ADDI rd, rs1, 0 is used to implement the MV rd, rs1 assembler pseudoinstruction.

ISA: rv32

", "tooltip": "ADDI adds the sign-extended 12-bit immediate to register rs1. Arithmetic overflow is ignored and the result is simply the low XLEN bits of the result. ADDI rd, rs1, 0 is used to implement the MV rd, rs1 assembler pseudoinstruction.\n\n\n\n(ISA: rv32)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#integer-register-immediate-instructions" }; case "ADDIW": return { "html": "

ADDIW rd, rs1, imm12

ADDIW is an RV64I instruction that adds the sign-extended 12-bit immediate to register rs1 and produces the proper sign-extension of a 32-bit result in rd. Overflows are ignored and the result is the low 32 bits of the result sign-extended to 64 bits. Note, ADDIW rd, rs1, 0 writes the sign-extension of the lower 32 bits of register rs1 into register rd (assembler pseudoinstruction SEXT.W).

ISA: rv64

", "tooltip": "ADDIW is an RV64I instruction that adds the sign-extended 12-bit immediate to register rs1 and produces the proper sign-extension of a 32-bit result in rd. Overflows are ignored and the result is the low 32 bits of the result sign-extended to 64 bits. Note, ADDIW rd, rs1, 0 writes the sign-extension of the lower 32 bits of register rs1 into register rd (assembler pseudoinstruction SEXT.W).\n\n\n\n(ISA: rv64)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv64.html#integer-register-immediate-instructions" }; case "ADDW": return { "html": "

ADDW rd, rs1, rs2

ADDW and SUBW are RV64I-only instructions that are defined analogously to ADD and SUB but operate on 32-bit values and produce signed 32-bit results. Overflows are ignored, and the low 32-bits of the result is sign-extended to 64-bits and written to the destination register.

ISA: rv64

", "tooltip": "ADDW and SUBW are RV64I-only instructions that are defined analogously to ADD and SUB but operate on 32-bit values and produce signed 32-bit results. Overflows are ignored, and the low 32-bits of the result is sign-extended to 64-bits and written to the destination register.\n\n\n\n(ISA: rv64)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#integer-register-register-operations" }; case "AES32DSI": return { "html": "

AES32DSI rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "AES32DSMI": return { "html": "

AES32DSMI rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "AES32ESI": return { "html": "

AES32ESI rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "AES32ESMI": return { "html": "

AES32ESMI rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "AES64DS": return { "html": "

AES64DS rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "AES64DSM": return { "html": "

AES64DSM rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "AES64ES": return { "html": "

AES64ES rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "AES64ESM": return { "html": "

AES64ESM rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "AES64IM": return { "html": "

AES64IM rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "AES64KS1I": return { "html": "

AES64KS1I rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "AES64KS2": return { "html": "

AES64KS2 rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "AMOADD.D": return { "html": "

AMOADD.D rd, rs1, rs2

The atomic memory operation (AMO) instructions perform read-modify-write operations for multiprocessor synchronization and are encoded with an R-type instruction format. These AMO instructions atomically load a data value from the address in rs1, place the value into register rd, apply a binary operator to the loaded value and the original value in rs2, then store the result back to the original address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory. For RV64, 32-bit AMOs always sign-extend the value placed in rd, and ignore the upper 32 bits of the original value of rs2.

ISA: a

", "tooltip": "The atomic memory operation (AMO) instructions perform read-modify-write operations for multiprocessor synchronization and are encoded with an R-type instruction format. These AMO instructions atomically load a data value from the address in rs1, place the value into register rd, apply a binary operator to the loaded value and the original value in rs2, then store the result back to the original address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory. For RV64, 32-bit AMOs always sign-extend the value placed in rd, and ignore the upper 32 bits of the original value of rs2.\n\n\n\n(ISA: a)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/a.html#sec:amo" }; case "AMOADD.W": return { "html": "

AMOADD.W rd, rs1, rs2

ISA: a

AMOAND.D rd, rs1, rs2

ISA: a

AMOAND.W rd, rs1, rs2

ISA: a

AMOMAX.D rd, rs1, rs2

ISA: a

AMOMAX.W rd, rs1, rs2

ISA: a

AMOMAXU.D rd, rs1, rs2

ISA: a

AMOMAXU.W rd, rs1, rs2

ISA: a

AMOMIN.D rd, rs1, rs2

ISA: a

AMOMIN.W rd, rs1, rs2

ISA: a

AMOMINU.D rd, rs1, rs2

ISA: a

AMOMINU.W rd, rs1, rs2

ISA: a

AMOOR.D rd, rs1, rs2

ISA: a

AMOOR.W rd, rs1, rs2

ISA: a

AMOSWAP.D rd, rs1, rs2

ISA: a

AMOSWAP.W rd, rs1, rs2

ISA: a

AMOXOR.D rd, rs1, rs2

ISA: a

AMOXOR.W rd, rs1, rs2

ISA: a

AND rd, rs1, rs2

ADD performs the addition of rs1 and rs2. SUB performs the subtraction of rs2 from rs1. Overflows are ignored and the low XLEN bits of results are written to the destination rd. SLT and SLTU perform signed and unsigned compares respectively, writing 1 to rd if rs1 < rs2, 0 otherwise. Note, SLTU rd, x0, rs2 sets rd to 1 if rs2 is not equal to zero, otherwise sets rd to zero (assembler pseudoinstruction SNEZ rd, rs). AND, OR, and XOR perform bitwise logical operations.

ISA: rv32

ANDI rd, rs1, imm12

ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs a bitwise logical inversion of register rs1 (assembler pseudoinstruction NOT rd, rs).

ISA: rv32

", "tooltip": "ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs a bitwise logical inversion of register rs1 (assembler pseudoinstruction NOT rd, rs).\n\n\n\n(ISA: rv32)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#integer-register-immediate-instructions" }; case "ANDN": return { "html": "

ANDN rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "AUIPC": return { "html": "

AUIPC rd, imm20

AUIPC (add upper immediate to pc) is used to build pc-relative addresses and uses the U-type format. AUIPC forms a 32-bit offset from the U-immediate, filling in the lowest 12 bits with zeros, adds this offset to the address of the AUIPC instruction, then places the result in register rd.
The AUIPC instruction supports two-instruction sequences to access arbitrary offsets from the PC for both control-flow transfers and data accesses. The combination of an AUIPC and the 12-bit immediate in a JALR can transfer control to any 32-bit PC-relative address, while an AUIPC plus the 12-bit immediate offset in regular load or store instructions can access any 32-bit PC-relative data address.

ISA: rv32

", "tooltip": "AUIPC (add upper immediate to pc) is used to build pc-relative addresses and uses the U-type format. AUIPC forms a 32-bit offset from the U-immediate, filling in the lowest 12 bits with zeros, adds this offset to the address of the AUIPC instruction, then places the result in register rd.\nThe AUIPC instruction supports two-instruction sequences to access arbitrary offsets from the PC for both control-flow transfers and data accesses. The combination of an AUIPC and the 12-bit immediate in a JALR can transfer control to any 32-bit PC-relative address, while an AUIPC plus the 12-bit immediate offset in regular load or store instructions can access any 32-bit PC-relative data address.\n\n\n\n(ISA: rv32)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#integer-register-immediate-instructions" }; case "BCLR": return { "html": "

BCLR rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "BCLRI": return { "html": "

BCLRI rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "BEQ": return { "html": "

BEQ rs1, rs2, bimm12

Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU, BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU, respectively.

ISA: rv32

", "tooltip": "Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU, BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU, respectively.\n\n\n\n(ISA: rv32)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#conditional-branches" }; case "BEQZ": return { "html": "

BEQZ rs, offset

Equivalent ASM:

beq rs, x0, offset

ISA: (pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\nbeq rs, x0, offset\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "BEXT": return { "html": "

BEXT rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "BEXTI": return { "html": "

BEXTI rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "BGE": return { "html": "

BGE rs1, rs2, bimm12

Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU, BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU, respectively.

ISA: rv32

BGEU rs1, rs2, bimm12

Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU, BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU, respectively.

ISA: rv32

BGEZ rs, offset

Equivalent ASM:

bge rs, x0, offset

ISA: (pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\nbge rs, x0, offset\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "BGT": return { "html": "

BGT rs, rt, offset

Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU, BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU, respectively.

Equivalent ASM:

blt rt, rs, offset

ISA: rv32(pseudo)

", "tooltip": "Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU, BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU, respectively.\n\nEquivalent ASM:\n\nblt rt, rs, offset\n\n(ISA: rv32(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#conditional-branches" }; case "BGTU": return { "html": "

BGTU rs, rt, offset

Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU, BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU, respectively.

Equivalent ASM:

bltu rt, rs, offset

ISA: rv32(pseudo)

", "tooltip": "Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU, BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU, respectively.\n\nEquivalent ASM:\n\nbltu rt, rs, offset\n\n(ISA: rv32(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#conditional-branches" }; case "BGTZ": return { "html": "

BGTZ rs, offset

Equivalent ASM:

blt x0, rs, offset

ISA: (pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\nblt x0, rs, offset\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "BINV": return { "html": "

BINV rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "BINVI": return { "html": "

BINVI rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "BLE": return { "html": "

BLE rs, rt, offset

Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU, BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU, respectively.

Equivalent ASM:

bge rt, rs, offset

ISA: rv32(pseudo)

", "tooltip": "Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU, BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU, respectively.\n\nEquivalent ASM:\n\nbge rt, rs, offset\n\n(ISA: rv32(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#conditional-branches" }; case "BLEU": return { "html": "

BLEU rs, rt, offset

Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU, BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU, respectively.

Equivalent ASM:

bgeu rt, rs, offset

ISA: rv32(pseudo)

", "tooltip": "Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU, BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU, respectively.\n\nEquivalent ASM:\n\nbgeu rt, rs, offset\n\n(ISA: rv32(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#conditional-branches" }; case "BLEZ": return { "html": "

BLEZ rs, offset

Equivalent ASM:

bge x0, rs, offset

ISA: (pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\nbge x0, rs, offset\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "BLT": return { "html": "

BLT rs1, rs2, bimm12

Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU, BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU, respectively.

ISA: rv32

BLTU rs1, rs2, bimm12

Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU, BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU, respectively.
Signed array bounds may be checked with a single BLTU instruction, since any negative index will compare greater than any nonnegative bound.

ISA: rv32

", "tooltip": "Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU, BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU, respectively.\nSigned array bounds may be checked with a single BLTU instruction, since any negative index will compare greater than any nonnegative bound.\n\n\n\n(ISA: rv32)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#conditional-branches" }; case "BLTZ": return { "html": "

BLTZ rs, offset

Equivalent ASM:

blt rs, x0, offset

ISA: (pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\nblt rs, x0, offset\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "BNE": return { "html": "

BNE rs1, rs2, bimm12

Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU, BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU, respectively.

ISA: rv32

BNEZ rs, offset

Equivalent ASM:

bne rs, x0, offset

ISA: (pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\nbne rs, x0, offset\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "BREV8": return { "html": "

BREV8 rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "BSET": return { "html": "

BSET rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "BSETI": return { "html": "

BSETI rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "C.ADD": return { "html": "

C.ADD rd_rs1, c_rs2_n0

C.ADD adds the values in registers rd and rs2 and writes the result to register rd. C.ADD expands into add rd, rd, rs2. C.ADD is only valid when rs2 x0; the code points with rs2 = x0 correspond to the C.JALR and C.EBREAK instructions. The code points with rs2 x0 and rd = x0 are HINTs.

ISA: c

", "tooltip": "C.ADD adds the values in registers rd and rs2 and writes the result to register rd. C.ADD expands into add rd, rd, rs2. C.ADD is only valid when rs2 x0; the code points with rs2 = x0 correspond to the C.JALR and C.EBREAK instructions. The code points with rs2 x0 and rd = x0 are HINTs.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#integer-register-register-operations" }; case "C.ADDI": return { "html": "

C.ADDI rd_rs1_n0, c_nzimm6, c_nzimm6

C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd. C.ADDI expands into addi rd, rd, nzimm. C.ADDI is only valid when rd x0 and nzimm 0. The code points with rd=x0 encode the C.NOP instruction; the remaining code points with nzimm=0 encode HINTs.

ISA: c

", "tooltip": "C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd. C.ADDI expands into addi rd, rd, nzimm. C.ADDI is only valid when rd x0 and nzimm 0. The code points with rd=x0 encode the C.NOP instruction; the remaining code points with nzimm=0 encode HINTs.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#integer-register-immediate-operations" }; case "C.ADDI16SP": case "ADDI16SP": return { "html": "

C.ADDI16SP c_nzimm10

C.LUI loads the non-zero 6-bit immediate field into bits 17-12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. C.LUI expands into lui rd, nzimm. C.LUI is only valid when rd {x0,x2}, and when the immediate is not equal to zero. The code points with nzimm=0 are reserved; the remaining code points with rd=x0 are HINTs; and the remaining code points with rd=x2 correspond to the C.ADDI16SP instruction.

ISA: c

", "tooltip": "C.LUI loads the non-zero 6-bit immediate field into bits 17-12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. C.LUI expands into lui rd, nzimm. C.LUI is only valid when rd {x0,x2}, and when the immediate is not equal to zero. The code points with nzimm=0 are reserved; the remaining code points with rd=x0 are HINTs; and the remaining code points with rd=x2 correspond to the C.ADDI16SP instruction.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#integer-constant-generation-instructions" }; case "C.ADDI4SPN": case "ADDI4SPN": return { "html": "

C.ADDI4SPN rd_p, c_nzuimm10

C.ADDI4SPN is a CIW-format instruction that adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd'. This instruction is used to generate pointers to stack-allocated variables, and expands to addi rd', x2, nzuimm. C.ADDI4SPN is only valid when nzuimm 0; the code points with nzuimm=0 are reserved.

ISA: c

", "tooltip": "C.ADDI4SPN is a CIW-format instruction that adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd'. This instruction is used to generate pointers to stack-allocated variables, and expands to addi rd', x2, nzuimm. C.ADDI4SPN is only valid when nzuimm 0; the code points with nzuimm=0 are reserved.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#integer-register-immediate-operations" }; case "C.ADDIW": return { "html": "

C.ADDIW rd_rs1_n0, c_imm6

C.ADDIW is an RV64C/RV128C-only instruction that performs the same computation but produces a 32-bit result, then sign-extends result to 64 bits. C.ADDIW expands into addiw rd, rd, imm. The immediate can be zero for C.ADDIW, where this corresponds to sext.w rd. C.ADDIW is only valid when rd x0; the code points with rd=x0 are reserved.

ISA: c

", "tooltip": "C.ADDIW is an RV64C/RV128C-only instruction that performs the same computation but produces a 32-bit result, then sign-extends result to 64 bits. C.ADDIW expands into addiw rd, rd, imm. The immediate can be zero for C.ADDIW, where this corresponds to sext.w rd. C.ADDIW is only valid when rd x0; the code points with rd=x0 are reserved.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#integer-register-immediate-operations" }; case "C.ADDW": return { "html": "

C.ADDW rd_rs1_p, rs2_p

C.ADDW is an RV64C/RV128C-only instruction that adds the values in registers rd' and rs2', then sign-extends the lower 32 bits of the sum before writing the result to register rd'. C.ADDW expands into addw rd', rd', rs2'.

ISA: c

", "tooltip": "C.ADDW is an RV64C/RV128C-only instruction that adds the values in registers rd' and rs2', then sign-extends the lower 32 bits of the sum before writing the result to register rd'. C.ADDW expands into addw rd', rd', rs2'.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#integer-register-register-operations" }; case "C.AND": return { "html": "

C.AND rd_rs1_p, rs2_p

C.AND computes the bitwise AND of the values in registers rd' and rs2', then writes the result to register rd'. C.AND expands into and rd', rd', rs2'.

ISA: c

", "tooltip": "C.AND computes the bitwise AND of the values in registers rd' and rs2', then writes the result to register rd'. C.AND expands into and rd', rd', rs2'.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#integer-register-register-operations" }; case "C.ANDI": return { "html": "

C.ANDI rd_rs1_p, c_imm6

C.ANDI is a CB-format instruction that computes the bitwise AND of the value in register rd' and the sign-extended 6-bit immediate, then writes the result to rd'. C.ANDI expands to andi rd', rd', imm.

ISA: c

", "tooltip": "C.ANDI is a CB-format instruction that computes the bitwise AND of the value in register rd' and the sign-extended 6-bit immediate, then writes the result to rd'. C.ANDI expands to andi rd', rd', imm.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#integer-register-immediate-operations" }; case "C.BEQZ": return { "html": "

C.BEQZ rs1_p, c_bimm9

C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a \u00b1256B range. C.BEQZ takes the branch if the value in register rs1' is zero. It expands to beq rs1', x0, offset.

ISA: c

", "tooltip": "C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a \u00b1256B range. C.BEQZ takes the branch if the value in register rs1' is zero. It expands to beq rs1', x0, offset.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#control-transfer-instructions" }; case "C.BNEZ": return { "html": "

C.BNEZ rs1_p, c_bimm9

C.BNEZ is defined analogously, but it takes the branch if rs1' contains a nonzero value. It expands to bne rs1', x0, offset.

ISA: c

", "tooltip": "C.BNEZ is defined analogously, but it takes the branch if rs1' contains a nonzero value. It expands to bne rs1', x0, offset.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#control-transfer-instructions" }; case "C.EBREAK": return { "html": "

C.EBREAK

C.ADD adds the values in registers rd and rs2 and writes the result to register rd. C.ADD expands into add rd, rd, rs2. C.ADD is only valid when rs2 x0; the code points with rs2 = x0 correspond to the C.JALR and C.EBREAK instructions. The code points with rs2 x0 and rd = x0 are HINTs.

ISA: c

C.FLD rd_p, rs1_p, c_uimm8

C.FLD is an RV32DC/RV64DC-only instruction that loads a double-precision floating-point value from memory into floating-point register rd'. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1'. It expands to fld rd', offset(rs1').

ISA: c

", "tooltip": "C.FLD is an RV32DC/RV64DC-only instruction that loads a double-precision floating-point value from memory into floating-point register rd'. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1'. It expands to fld rd', offset(rs1').\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#register-based-loads-and-stores" }; case "C.FLDSP": case "FLDSP": return { "html": "

C.FLDSP rd, c_uimm9sp

C.FLDSP is an RV32DC/RV64DC-only instruction that loads a double-precision floating-point value from memory into floating-point register rd. It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to fld rd, offset(x2).

ISA: c

", "tooltip": "C.FLDSP is an RV32DC/RV64DC-only instruction that loads a double-precision floating-point value from memory into floating-point register rd. It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to fld rd, offset(x2).\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#stack-pointer-based-loads-and-stores" }; case "C.FLW": return { "html": "

C.FLW rd_p, rs1_p, c_uimm7

C.FLW is an RV32FC-only instruction that loads a single-precision floating-point value from memory into floating-point register rd'. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1'. It expands to flw rd', offset(rs1').

ISA: c

", "tooltip": "C.FLW is an RV32FC-only instruction that loads a single-precision floating-point value from memory into floating-point register rd'. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1'. It expands to flw rd', offset(rs1').\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#register-based-loads-and-stores" }; case "C.FLWSP": case "FLWSP": return { "html": "

C.FLWSP rd, c_uimm8sp

C.FLWSP is an RV32FC-only instruction that loads a single-precision floating-point value from memory into floating-point register rd. It computes its effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to flw rd, offset(x2).

ISA: c

", "tooltip": "C.FLWSP is an RV32FC-only instruction that loads a single-precision floating-point value from memory into floating-point register rd. It computes its effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to flw rd, offset(x2).\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#stack-pointer-based-loads-and-stores" }; case "C.FSD": return { "html": "

C.FSD rs1_p, rs2_p, c_uimm8

C.FSD is an RV32DC/RV64DC-only instruction that stores a double-precision floating-point value in floating-point register rs2' to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1'. It expands to fsd rs2', offset(rs1').

ISA: c

", "tooltip": "C.FSD is an RV32DC/RV64DC-only instruction that stores a double-precision floating-point value in floating-point register rs2' to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1'. It expands to fsd rs2', offset(rs1').\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#register-based-loads-and-stores" }; case "C.FSDSP": case "FSDSP": return { "html": "

C.FSDSP c_rs2, c_uimm9sp_s

C.FSDSP is an RV32DC/RV64DC-only instruction that stores a double-precision floating-point value in floating-point register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to fsd rs2, offset(x2).

ISA: c

", "tooltip": "C.FSDSP is an RV32DC/RV64DC-only instruction that stores a double-precision floating-point value in floating-point register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to fsd rs2, offset(x2).\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#stack-pointer-based-loads-and-stores" }; case "C.FSW": return { "html": "

C.FSW rs1_p, rs2_p, c_uimm7

C.FSW is an RV32FC-only instruction that stores a single-precision floating-point value in floating-point register rs2' to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1'. It expands to fsw rs2', offset(rs1').

ISA: c

", "tooltip": "C.FSW is an RV32FC-only instruction that stores a single-precision floating-point value in floating-point register rs2' to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1'. It expands to fsw rs2', offset(rs1').\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#register-based-loads-and-stores" }; case "C.FSWSP": case "FSWSP": return { "html": "

C.FSWSP c_rs2, c_uimm8sp_s

C.FSWSP is an RV32FC-only instruction that stores a single-precision floating-point value in floating-point register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to fsw rs2, offset(x2).

ISA: c

", "tooltip": "C.FSWSP is an RV32FC-only instruction that stores a single-precision floating-point value in floating-point register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to fsw rs2, offset(x2).\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#stack-pointer-based-loads-and-stores" }; case "C.J": return { "html": "

C.J c_imm12

C.J performs an unconditional control transfer. The offset is sign-extended and added to the pc to form the jump target address. C.J can therefore target a \u00b12KiB range. C.J expands to jal x0, offset.
C.JAL is an RV32C-only instruction that performs the same operation as C.J, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1. C.JAL expands to jal x1, offset.

ISA: c

", "tooltip": "C.J performs an unconditional control transfer. The offset is sign-extended and added to the pc to form the jump target address. C.J can therefore target a \u00b12KiB range. C.J expands to jal x0, offset.\nC.JAL is an RV32C-only instruction that performs the same operation as C.J, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1. C.JAL expands to jal x1, offset.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#control-transfer-instructions" }; case "C.JAL": return { "html": "

C.JAL c_imm12

C.JAL is an RV32C-only instruction that performs the same operation as C.J, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1. C.JAL expands to jal x1, offset.

ISA: c

", "tooltip": "C.JAL is an RV32C-only instruction that performs the same operation as C.J, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1. C.JAL expands to jal x1, offset.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#control-transfer-instructions" }; case "C.JALR": return { "html": "

C.JALR c_rs1_n0

C.ADD adds the values in registers rd and rs2 and writes the result to register rd. C.ADD expands into add rd, rd, rs2. C.ADD is only valid when rs2 x0; the code points with rs2 = x0 correspond to the C.JALR and C.EBREAK instructions. The code points with rs2 x0 and rd = x0 are HINTs.

ISA: c

C.JR rs1_n0

C.MV copies the value in register rs2 into register rd. C.MV expands into add rd, x0, rs2. C.MV is only valid when rs2 x0; the code points with rs2 = x0 correspond to the C.JR instruction. The code points with rs2 x0 and rd = x0 are HINTs.

ISA: c

", "tooltip": "C.MV copies the value in register rs2 into register rd. C.MV expands into add rd, x0, rs2. C.MV is only valid when rs2 x0; the code points with rs2 = x0 correspond to the C.JR instruction. The code points with rs2 x0 and rd = x0 are HINTs.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#integer-register-register-operations" }; case "C.LBU": return { "html": "

C.LBU rd_p, rs1_p, c_uimm2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "C.LD": return { "html": "

C.LD rd_p, rs1_p, c_uimm8

C.LD is an RV64C/RV128C-only instruction that loads a 64-bit value from memory into register rd'. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1'. It expands to ld rd', offset(rs1').

ISA: c

", "tooltip": "C.LD is an RV64C/RV128C-only instruction that loads a 64-bit value from memory into register rd'. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1'. It expands to ld rd', offset(rs1').\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#register-based-loads-and-stores" }; case "C.LDSP": case "LDSP": return { "html": "

C.LDSP rd_n0, c_uimm9sp

C.LDSP is an RV64C/RV128C-only instruction that loads a 64-bit value from memory into register rd. It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to ld rd, offset(x2). C.LDSP is only valid when rd x0; the code points with rd = x0 are reserved.

ISA: c

", "tooltip": "C.LDSP is an RV64C/RV128C-only instruction that loads a 64-bit value from memory into register rd. It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to ld rd, offset(x2). C.LDSP is only valid when rd x0; the code points with rd = x0 are reserved.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#stack-pointer-based-loads-and-stores" }; case "C.LH": return { "html": "

C.LH rd_p, rs1_p, c_uimm1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "C.LHU": return { "html": "

C.LHU rd_p, rs1_p, c_uimm1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "C.LI": return { "html": "

C.LI rd, c_imm6

C.LI loads the sign-extended 6-bit immediate, imm, into register rd. C.LI expands into addi rd, x0, imm. C.LI is only valid when rd x0; the code points with rd=x0 encode HINTs.

ISA: c

", "tooltip": "C.LI loads the sign-extended 6-bit immediate, imm, into register rd. C.LI expands into addi rd, x0, imm. C.LI is only valid when rd x0; the code points with rd=x0 encode HINTs.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#integer-constant-generation-instructions" }; case "C.LUI": return { "html": "

C.LUI rd_n2, c_nzimm18

C.LUI loads the non-zero 6-bit immediate field into bits 17-12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. C.LUI expands into lui rd, nzimm. C.LUI is only valid when rd {x0,x2}, and when the immediate is not equal to zero. The code points with nzimm=0 are reserved; the remaining code points with rd=x0 are HINTs; and the remaining code points with rd=x2 correspond to the C.ADDI16SP instruction.

ISA: c

C.LW rd_p, rs1_p, c_uimm7

C.LW loads a 32-bit value from memory into register rd'. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1'. It expands to lw rd', offset(rs1').

ISA: c

", "tooltip": "C.LW loads a 32-bit value from memory into register rd'. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1'. It expands to lw rd', offset(rs1').\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#register-based-loads-and-stores" }; case "C.LWSP": case "LWSP": return { "html": "

C.LWSP rd_n0, c_uimm8sp

C.LWSP loads a 32-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to lw rd, offset(x2). C.LWSP is only valid when rd x0; the code points with rd = x0 are reserved.

ISA: c

", "tooltip": "C.LWSP loads a 32-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to lw rd, offset(x2). C.LWSP is only valid when rd x0; the code points with rd = x0 are reserved.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#stack-pointer-based-loads-and-stores" }; case "C.MUL": return { "html": "

C.MUL rd_rs1_p, rs2_p

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "C.MV": return { "html": "

C.MV rd, c_rs2_n0

C.MV copies the value in register rs2 into register rd. C.MV expands into add rd, x0, rs2. C.MV is only valid when rs2 x0; the code points with rs2 = x0 correspond to the C.JR instruction. The code points with rs2 x0 and rd = x0 are HINTs.
C.MV expands to a different instruction than the canonical MV pseudoinstruction, which instead uses ADDI. Implementations that handle MV specially, e.g. using register-renaming hardware, may find it more convenient to expand C.MV to MV instead of ADD, at slight additional hardware cost.

ISA: c

", "tooltip": "C.MV copies the value in register rs2 into register rd. C.MV expands into add rd, x0, rs2. C.MV is only valid when rs2 x0; the code points with rs2 = x0 correspond to the C.JR instruction. The code points with rs2 x0 and rd = x0 are HINTs.\nC.MV expands to a different instruction than the canonical MV pseudoinstruction, which instead uses ADDI. Implementations that handle MV specially, e.g. using register-renaming hardware, may find it more convenient to expand C.MV to MV instead of ADD, at slight additional hardware cost.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#integer-register-register-operations" }; case "C.NOP": return { "html": "

C.NOP c_nzimm6

C.NOP is a CI-format instruction that does not change any user-visible state, except for advancing the pc and incrementing any applicable performance counters. C.NOP expands to nop. C.NOP is only valid when imm=0; the code points with imm 0 encode HINTs.

ISA: c

", "tooltip": "C.NOP is a CI-format instruction that does not change any user-visible state, except for advancing the pc and incrementing any applicable performance counters. C.NOP expands to nop. C.NOP is only valid when imm=0; the code points with imm 0 encode HINTs.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#nop-instruction" }; case "C.NOT": return { "html": "

C.NOT rd_rs1_p

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "C.OR": return { "html": "

C.OR rd_rs1_p, rs2_p

C.OR computes the bitwise OR of the values in registers rd' and rs2', then writes the result to register rd'. C.OR expands into or rd', rd', rs2'.

ISA: c

", "tooltip": "C.OR computes the bitwise OR of the values in registers rd' and rs2', then writes the result to register rd'. C.OR expands into or rd', rd', rs2'.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#integer-register-register-operations" }; case "C.SB": return { "html": "

C.SB rs2_p, rs1_p, c_uimm2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "C.SD": return { "html": "

C.SD rs1_p, rs2_p, c_uimm8

C.SD is an RV64C/RV128C-only instruction that stores a 64-bit value in register rs2' to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1'. It expands to sd rs2', offset(rs1').

ISA: c

", "tooltip": "C.SD is an RV64C/RV128C-only instruction that stores a 64-bit value in register rs2' to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1'. It expands to sd rs2', offset(rs1').\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#register-based-loads-and-stores" }; case "C.SDSP": case "SDSP": return { "html": "

C.SDSP c_rs2, c_uimm9sp_s

C.SDSP is an RV64C/RV128C-only instruction that stores a 64-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to sd rs2, offset(x2).

ISA: c

", "tooltip": "C.SDSP is an RV64C/RV128C-only instruction that stores a 64-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to sd rs2, offset(x2).\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#stack-pointer-based-loads-and-stores" }; case "C.SEXT.B": return { "html": "

C.SEXT.B rd_rs1_p

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "C.SEXT.H": return { "html": "

C.SEXT.H rd_rs1_p

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "C.SH": return { "html": "

C.SH rs2_p, rs1_p, c_uimm1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "C.SLLI": return { "html": "

C.SLLI rd_rs1_n0, c_nzuimm6

C.SLLI is a CI-format instruction that performs a logical left shift of the value in register rd then writes the result to rd. The shift amount is encoded in the shamt field. For RV128C, a shift amount of zero is used to encode a shift of 64. C.SLLI expands into slli rd, rd, shamt, except for RV128C with shamt=0, which expands to slli rd, rd, 64.

ISA: c

", "tooltip": "C.SLLI is a CI-format instruction that performs a logical left shift of the value in register rd then writes the result to rd. The shift amount is encoded in the shamt field. For RV128C, a shift amount of zero is used to encode a shift of 64. C.SLLI expands into slli rd, rd, shamt, except for RV128C with shamt=0, which expands to slli rd, rd, 64.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#integer-register-immediate-operations" }; case "C.SLLI_RV32": return { "html": "

C.SLLI_RV32 rd_rs1_n0, c_nzuimm6lo

ISA: c

", "tooltip": "\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "C.SRAI": return { "html": "

C.SRAI rd_rs1_p, c_nzuimm6

C.SRAI is defined analogously to C.SRLI, but instead performs an arithmetic right shift. C.SRAI expands to srai rd', rd', shamt.

ISA: c

", "tooltip": "C.SRAI is defined analogously to C.SRLI, but instead performs an arithmetic right shift. C.SRAI expands to srai rd', rd', shamt.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#integer-register-immediate-operations" }; case "C.SRAI_RV32": return { "html": "

C.SRAI_RV32 rd_rs1_p, c_nzuimm5

ISA: c

", "tooltip": "\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "C.SRLI": return { "html": "

C.SRLI rd_rs1_p, c_nzuimm6

C.SRLI is a CB-format instruction that performs a logical right shift of the value in register rd' then writes the result to rd'. The shift amount is encoded in the shamt field. For RV128C, a shift amount of zero is used to encode a shift of 64. Furthermore, the shift amount is sign-extended for RV128C, and so the legal shift amounts are 1-31, 64, and 96-127. C.SRLI expands into srli rd', rd', shamt, except for RV128C with shamt=0, which expands to srli rd', rd', 64.
C.SRAI is defined analogously to C.SRLI, but instead performs an arithmetic right shift. C.SRAI expands to srai rd', rd', shamt.

ISA: c

", "tooltip": "C.SRLI is a CB-format instruction that performs a logical right shift of the value in register rd' then writes the result to rd'. The shift amount is encoded in the shamt field. For RV128C, a shift amount of zero is used to encode a shift of 64. Furthermore, the shift amount is sign-extended for RV128C, and so the legal shift amounts are 1-31, 64, and 96-127. C.SRLI expands into srli rd', rd', shamt, except for RV128C with shamt=0, which expands to srli rd', rd', 64.\nC.SRAI is defined analogously to C.SRLI, but instead performs an arithmetic right shift. C.SRAI expands to srai rd', rd', shamt.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#integer-register-immediate-operations" }; case "C.SRLI_RV32": return { "html": "

C.SRLI_RV32 rd_rs1_p, c_nzuimm5

ISA: c

", "tooltip": "\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "C.SUB": return { "html": "

C.SUB rd_rs1_p, rs2_p

C.SUB subtracts the value in register rs2' from the value in register rd', then writes the result to register rd'. C.SUB expands into sub rd', rd', rs2'.

ISA: c

", "tooltip": "C.SUB subtracts the value in register rs2' from the value in register rd', then writes the result to register rd'. C.SUB expands into sub rd', rd', rs2'.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#integer-register-register-operations" }; case "C.SUBW": return { "html": "

C.SUBW rd_rs1_p, rs2_p

C.SUBW is an RV64C/RV128C-only instruction that subtracts the value in register rs2' from the value in register rd', then sign-extends the lower 32 bits of the difference before writing the result to register rd'. C.SUBW expands into subw rd', rd', rs2'.

ISA: c

", "tooltip": "C.SUBW is an RV64C/RV128C-only instruction that subtracts the value in register rs2' from the value in register rd', then sign-extends the lower 32 bits of the difference before writing the result to register rd'. C.SUBW expands into subw rd', rd', rs2'.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#integer-register-register-operations" }; case "C.SW": return { "html": "

C.SW rs1_p, rs2_p, c_uimm7

C.SW stores a 32-bit value in register rs2' to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1'. It expands to sw rs2', offset(rs1').

ISA: c

", "tooltip": "C.SW stores a 32-bit value in register rs2' to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1'. It expands to sw rs2', offset(rs1').\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#register-based-loads-and-stores" }; case "C.SWSP": case "SWSP": return { "html": "

C.SWSP c_rs2, c_uimm8sp_s

C.SWSP stores a 32-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to sw rs2, offset(x2).

ISA: c

", "tooltip": "C.SWSP stores a 32-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to sw rs2, offset(x2).\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#stack-pointer-based-loads-and-stores" }; case "C.XOR": return { "html": "

C.XOR rd_rs1_p, rs2_p

C.XOR computes the bitwise XOR of the values in registers rd' and rs2', then writes the result to register rd'. C.XOR expands into xor rd', rd', rs2'.

ISA: c

", "tooltip": "C.XOR computes the bitwise XOR of the values in registers rd' and rs2', then writes the result to register rd'. C.XOR expands into xor rd', rd', rs2'.\n\n\n\n(ISA: c)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/c.html#integer-register-register-operations" }; case "C.ZEXT.B": return { "html": "

C.ZEXT.B rd_rs1_p

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "C.ZEXT.H": return { "html": "

C.ZEXT.H rd_rs1_p

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "C.ZEXT.W": return { "html": "

C.ZEXT.W rd_rs1_p

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CALL": return { "html": "

CALL offset

Equivalent ASM:

auipc x1, offset[31:12]\njalr x1, x1, offset[11:0]

ISA: (pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\nauipc x1, offset[31:12]\njalr x1, x1, offset[11:0]\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CBO.CLEAN": return { "html": "

CBO.CLEAN rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CBO.FLUSH": return { "html": "

CBO.FLUSH rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CBO.INVAL": return { "html": "

CBO.INVAL rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CBO.ZERO": return { "html": "

CBO.ZERO rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CLMUL": return { "html": "

CLMUL rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CLMULH": return { "html": "

CLMULH rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CLMULR": return { "html": "

CLMULR rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CLZ": return { "html": "

CLZ rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CLZW": return { "html": "

CLZW rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CM.JALT": return { "html": "

CM.JALT

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CM.MVA01S": return { "html": "

CM.MVA01S

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CM.MVSA01": return { "html": "

CM.MVSA01

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CM.POP": return { "html": "

CM.POP c_spimm

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CM.POPRET": return { "html": "

CM.POPRET c_spimm

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CM.POPRETZ": return { "html": "

CM.POPRETZ c_spimm

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CM.PUSH": return { "html": "

CM.PUSH c_spimm

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CPOP": return { "html": "

CPOP rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CPOPW": return { "html": "

CPOPW rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CSRC": return { "html": "

CSRC csr, rs

Further assembler pseudoinstructions are defined to set and clear bits in the CSR when the old value is not required: CSRS/CSRC csr, rs1; CSRSI/CSRCI csr, uimm.

Equivalent ASM:

csrrc x0, csr, rs

ISA: csr(pseudo)

", "tooltip": "Further assembler pseudoinstructions are defined to set and clear bits in the CSR when the old value is not required: CSRS/CSRC csr, rs1; CSRSI/CSRCI csr, uimm.\n\nEquivalent ASM:\n\ncsrrc x0, csr, rs\n\n(ISA: csr(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/csr.html#csr-instructions" }; case "CSRCI": return { "html": "

CSRCI csr, imm

Further assembler pseudoinstructions are defined to set and clear bits in the CSR when the old value is not required: CSRS/CSRC csr, rs1; CSRSI/CSRCI csr, uimm.

Equivalent ASM:

csrrci x0, csr, imm

ISA: csr(pseudo)

", "tooltip": "Further assembler pseudoinstructions are defined to set and clear bits in the CSR when the old value is not required: CSRS/CSRC csr, rs1; CSRSI/CSRCI csr, uimm.\n\nEquivalent ASM:\n\ncsrrci x0, csr, imm\n\n(ISA: csr(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/csr.html#csr-instructions" }; case "CSRR": return { "html": "

CSRR rd, csr

The assembler pseudoinstruction to read a CSR, CSRR rd, csr, is encoded as CSRRS rd, csr, x0. The assembler pseudoinstruction to write a CSR, CSRW csr, rs1, is encoded as CSRRW x0, csr, rs1, while CSRWI csr, uimm, is encoded as CSRRWI x0, csr, uimm.

Equivalent ASM:

csrrs rd, csr, x0

ISA: csr(pseudo)

", "tooltip": "The assembler pseudoinstruction to read a CSR, CSRR rd, csr, is encoded as CSRRS rd, csr, x0. The assembler pseudoinstruction to write a CSR, CSRW csr, rs1, is encoded as CSRRW x0, csr, rs1, while CSRWI csr, uimm, is encoded as CSRRWI x0, csr, uimm.\n\nEquivalent ASM:\n\ncsrrs rd, csr, x0\n\n(ISA: csr(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/csr.html#csr-instructions" }; case "CSRRC": return { "html": "

CSRRC rd, rs1

The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be cleared in the CSR, if that CSR bit is writable. Other bits in the CSR are not explicitly written.
For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal instruction exceptions on accesses to read-only CSRs. Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields. Note that if rs1 specifies a register holding a zero value other than x0, the instruction will still attempt to write the unmodified value back to the CSR and will cause any attendant side effects. A CSRRW with rs1=x0 will attempt to write zero to the destination CSR.
The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal instruction exceptions on accesses to read-only CSRs. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.

ISA: csr

", "tooltip": "The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be cleared in the CSR, if that CSR bit is writable. Other bits in the CSR are not explicitly written.\nFor both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal instruction exceptions on accesses to read-only CSRs. Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields. Note that if rs1 specifies a register holding a zero value other than x0, the instruction will still attempt to write the unmodified value back to the CSR and will cause any attendant side effects. A CSRRW with rs1=x0 will attempt to write zero to the destination CSR.\nThe CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal instruction exceptions on accesses to read-only CSRs. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.\n\n\n\n(ISA: csr)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/csr.html#csr-instructions" }; case "CSRRCI": return { "html": "

CSRRCI rd, zimm

The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal instruction exceptions on accesses to read-only CSRs. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.

ISA: csr

", "tooltip": "The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal instruction exceptions on accesses to read-only CSRs. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.\n\n\n\n(ISA: csr)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/csr.html#csr-instructions" }; case "CSRRS": return { "html": "

CSRRS rd, rs1

The CSRRS (Atomic Read and Set Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are not explicitly written.
For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal instruction exceptions on accesses to read-only CSRs. Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields. Note that if rs1 specifies a register holding a zero value other than x0, the instruction will still attempt to write the unmodified value back to the CSR and will cause any attendant side effects. A CSRRW with rs1=x0 will attempt to write zero to the destination CSR.
The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal instruction exceptions on accesses to read-only CSRs. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.
The assembler pseudoinstruction to read a CSR, CSRR rd, csr, is encoded as CSRRS rd, csr, x0. The assembler pseudoinstruction to write a CSR, CSRW csr, rs1, is encoded as CSRRW x0, csr, rs1, while CSRWI csr, uimm, is encoded as CSRRWI x0, csr, uimm.

ISA: csr

", "tooltip": "The CSRRS (Atomic Read and Set Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are not explicitly written.\nFor both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal instruction exceptions on accesses to read-only CSRs. Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields. Note that if rs1 specifies a register holding a zero value other than x0, the instruction will still attempt to write the unmodified value back to the CSR and will cause any attendant side effects. A CSRRW with rs1=x0 will attempt to write zero to the destination CSR.\nThe CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal instruction exceptions on accesses to read-only CSRs. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.\nThe assembler pseudoinstruction to read a CSR, CSRR rd, csr, is encoded as CSRRS rd, csr, x0. The assembler pseudoinstruction to write a CSR, CSRW csr, rs1, is encoded as CSRRW x0, csr, rs1, while CSRWI csr, uimm, is encoded as CSRRWI x0, csr, uimm.\n\n\n\n(ISA: csr)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/csr.html#csr-instructions" }; case "CSRRSI": return { "html": "

CSRRSI rd, zimm

The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal instruction exceptions on accesses to read-only CSRs. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.

ISA: csr

CSRRW rd, rs1

The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in the CSRs and integer registers. CSRRW reads the old value of the CSR, zero-extends the value to XLEN bits, then writes it to integer register rd. The initial value in rs1 is written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read.
For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal instruction exceptions on accesses to read-only CSRs. Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields. Note that if rs1 specifies a register holding a zero value other than x0, the instruction will still attempt to write the unmodified value back to the CSR and will cause any attendant side effects. A CSRRW with rs1=x0 will attempt to write zero to the destination CSR.
The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal instruction exceptions on accesses to read-only CSRs. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.
The assembler pseudoinstruction to read a CSR, CSRR rd, csr, is encoded as CSRRS rd, csr, x0. The assembler pseudoinstruction to write a CSR, CSRW csr, rs1, is encoded as CSRRW x0, csr, rs1, while CSRWI csr, uimm, is encoded as CSRRWI x0, csr, uimm.

ISA: csr

", "tooltip": "The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in the CSRs and integer registers. CSRRW reads the old value of the CSR, zero-extends the value to XLEN bits, then writes it to integer register rd. The initial value in rs1 is written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read.\nFor both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal instruction exceptions on accesses to read-only CSRs. Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields. Note that if rs1 specifies a register holding a zero value other than x0, the instruction will still attempt to write the unmodified value back to the CSR and will cause any attendant side effects. A CSRRW with rs1=x0 will attempt to write zero to the destination CSR.\nThe CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal instruction exceptions on accesses to read-only CSRs. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.\nThe assembler pseudoinstruction to read a CSR, CSRR rd, csr, is encoded as CSRRS rd, csr, x0. The assembler pseudoinstruction to write a CSR, CSRW csr, rs1, is encoded as CSRRW x0, csr, rs1, while CSRWI csr, uimm, is encoded as CSRRWI x0, csr, uimm.\n\n\n\n(ISA: csr)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/csr.html#csr-instructions" }; case "CSRRWI": return { "html": "

CSRRWI rd, zimm

The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal instruction exceptions on accesses to read-only CSRs. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.
The assembler pseudoinstruction to read a CSR, CSRR rd, csr, is encoded as CSRRS rd, csr, x0. The assembler pseudoinstruction to write a CSR, CSRW csr, rs1, is encoded as CSRRW x0, csr, rs1, while CSRWI csr, uimm, is encoded as CSRRWI x0, csr, uimm.

ISA: csr

", "tooltip": "The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal instruction exceptions on accesses to read-only CSRs. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.\nThe assembler pseudoinstruction to read a CSR, CSRR rd, csr, is encoded as CSRRS rd, csr, x0. The assembler pseudoinstruction to write a CSR, CSRW csr, rs1, is encoded as CSRRW x0, csr, rs1, while CSRWI csr, uimm, is encoded as CSRRWI x0, csr, uimm.\n\n\n\n(ISA: csr)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/csr.html#csr-instructions" }; case "CSRS": return { "html": "

CSRS csr, rs

Further assembler pseudoinstructions are defined to set and clear bits in the CSR when the old value is not required: CSRS/CSRC csr, rs1; CSRSI/CSRCI csr, uimm.

Equivalent ASM:

csrrs x0, csr, rs

ISA: csr(pseudo)

", "tooltip": "Further assembler pseudoinstructions are defined to set and clear bits in the CSR when the old value is not required: CSRS/CSRC csr, rs1; CSRSI/CSRCI csr, uimm.\n\nEquivalent ASM:\n\ncsrrs x0, csr, rs\n\n(ISA: csr(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/csr.html#csr-instructions" }; case "CSRSI": return { "html": "

CSRSI csr, imm

Further assembler pseudoinstructions are defined to set and clear bits in the CSR when the old value is not required: CSRS/CSRC csr, rs1; CSRSI/CSRCI csr, uimm.

Equivalent ASM:

csrrsi x0, csr, imm

ISA: csr(pseudo)

", "tooltip": "Further assembler pseudoinstructions are defined to set and clear bits in the CSR when the old value is not required: CSRS/CSRC csr, rs1; CSRSI/CSRCI csr, uimm.\n\nEquivalent ASM:\n\ncsrrsi x0, csr, imm\n\n(ISA: csr(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/csr.html#csr-instructions" }; case "CSRW": return { "html": "

CSRW csr, rs

The assembler pseudoinstruction to read a CSR, CSRR rd, csr, is encoded as CSRRS rd, csr, x0. The assembler pseudoinstruction to write a CSR, CSRW csr, rs1, is encoded as CSRRW x0, csr, rs1, while CSRWI csr, uimm, is encoded as CSRRWI x0, csr, uimm.

Equivalent ASM:

csrrw x0, csr, rs

ISA: csr(pseudo)

", "tooltip": "The assembler pseudoinstruction to read a CSR, CSRR rd, csr, is encoded as CSRRS rd, csr, x0. The assembler pseudoinstruction to write a CSR, CSRW csr, rs1, is encoded as CSRRW x0, csr, rs1, while CSRWI csr, uimm, is encoded as CSRRWI x0, csr, uimm.\n\nEquivalent ASM:\n\ncsrrw x0, csr, rs\n\n(ISA: csr(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/csr.html#csr-instructions" }; case "CSRWI": return { "html": "

CSRWI csr, imm

The assembler pseudoinstruction to read a CSR, CSRR rd, csr, is encoded as CSRRS rd, csr, x0. The assembler pseudoinstruction to write a CSR, CSRW csr, rs1, is encoded as CSRRW x0, csr, rs1, while CSRWI csr, uimm, is encoded as CSRRWI x0, csr, uimm.

Equivalent ASM:

csrrwi x0, csr, imm

ISA: csr(pseudo)

", "tooltip": "The assembler pseudoinstruction to read a CSR, CSRR rd, csr, is encoded as CSRRS rd, csr, x0. The assembler pseudoinstruction to write a CSR, CSRW csr, rs1, is encoded as CSRRW x0, csr, rs1, while CSRWI csr, uimm, is encoded as CSRRWI x0, csr, uimm.\n\nEquivalent ASM:\n\ncsrrwi x0, csr, imm\n\n(ISA: csr(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/csr.html#csr-instructions" }; case "CTZ": return { "html": "

CTZ rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "CTZW": return { "html": "

CTZW rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "DIV": return { "html": "

DIV rd, rs1, rs2

DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by rs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division operation. For REM, the sign of the result equals the sign of the dividend.
If both the quotient and remainder are required from the same division, the recommended code sequence is: DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2 (rdq cannot be the same as rs1 or rs2). Microarchitectures can then fuse these into a single divide operation instead of performing two separate divides.
DIV[W]

ISA: m

", "tooltip": "DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by rs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division operation. For REM, the sign of the result equals the sign of the dividend.\nIf both the quotient and remainder are required from the same division, the recommended code sequence is: DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2 (rdq cannot be the same as rs1 or rs2). Microarchitectures can then fuse these into a single divide operation instead of performing two separate divides.\nDIV[W]\n\n\n\n(ISA: m)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/m.html#division-operations" }; case "DIVU": return { "html": "

DIVU rd, rs1, rs2

DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by rs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division operation. For REM, the sign of the result equals the sign of the dividend.
DIVU[W]

ISA: m

DIVUW rd, rs1, rs2

DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32 bits of rs2, treating them as signed and unsigned integers respectively, placing the 32-bit quotient in rd, sign-extended to 64 bits. REMW and REMUW are RV64 instructions that provide the corresponding signed and unsigned remainder operations respectively. Both REMW and REMUW always sign-extend the 32-bit result to 64 bits, including on a divide by zero.

ISA: m

", "tooltip": "DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32 bits of rs2, treating them as signed and unsigned integers respectively, placing the 32-bit quotient in rd, sign-extended to 64 bits. REMW and REMUW are RV64 instructions that provide the corresponding signed and unsigned remainder operations respectively. Both REMW and REMUW always sign-extend the 32-bit result to 64 bits, including on a divide by zero.\n\n\n\n(ISA: m)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/m.html#division-operations" }; case "DIVW": return { "html": "

DIVW rd, rs1, rs2

DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32 bits of rs2, treating them as signed and unsigned integers respectively, placing the 32-bit quotient in rd, sign-extended to 64 bits. REMW and REMUW are RV64 instructions that provide the corresponding signed and unsigned remainder operations respectively. Both REMW and REMUW always sign-extend the 32-bit result to 64 bits, including on a divide by zero.

ISA: m

DRET

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "EBREAK": return { "html": "

EBREAK

RV32I was designed to be sufficient to form a compiler target and to support modern operating system environments. The ISA was also designed to reduce the hardware required in a minimal implementation. RV32I contains 40 unique instructions, though a simple implementation might cover the ECALL/EBREAK instructions with a single SYSTEM hardware instruction that always traps and might be able to implement the FENCE instruction as a NOP, reducing base instruction count to 38 total. RV32I can emulate almost any other ISA extension (except the A extension, which requires additional hardware support for atomicity).

ISA: rv32

", "tooltip": "RV32I was designed to be sufficient to form a compiler target and to support modern operating system environments. The ISA was also designed to reduce the hardware required in a minimal implementation. RV32I contains 40 unique instructions, though a simple implementation might cover the ECALL/EBREAK instructions with a single SYSTEM hardware instruction that always traps and might be able to implement the FENCE instruction as a NOP, reducing base instruction count to 38 total. RV32I can emulate almost any other ISA extension (except the A extension, which requires additional hardware support for atomicity).\n\n\n\n(ISA: rv32)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#rv32" }; case "ECALL": return { "html": "

ECALL

RV32I was designed to be sufficient to form a compiler target and to support modern operating system environments. The ISA was also designed to reduce the hardware required in a minimal implementation. RV32I contains 40 unique instructions, though a simple implementation might cover the ECALL/EBREAK instructions with a single SYSTEM hardware instruction that always traps and might be able to implement the FENCE instruction as a NOP, reducing base instruction count to 38 total. RV32I can emulate almost any other ISA extension (except the A extension, which requires additional hardware support for atomicity).

ISA: rv32

FABS.D rd, rs

Equivalent ASM:

fsgnjx.d rd, rs, rs

ISA: d(pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\nfsgnjx.d rd, rs, rs\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FABS.S": return { "html": "

FABS.S rd, rs

Equivalent ASM:

fsgnjx.s rd, rs, rs

ISA: f(pseudo)

", "tooltip": "Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S rx, ry, ry moves ry to rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the negation of ry to rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry moves the absolute value of ry to rx (assembler pseudoinstruction FABS.S rx, ry).\n\nEquivalent ASM:\n\nfsgnjx.s rd, rs, rs\n\n(ISA: f(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-floating-point-conversion-and-move-instructions" }; case "FADD.D": return { "html": "

FADD.D rd, rs1, rs2

ISA: d

", "tooltip": "\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FADD.H": return { "html": "

FADD.H rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FADD.Q": return { "html": "

FADD.Q rd, rs1, rs2

ISA: q

", "tooltip": "\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FADD.S": return { "html": "

FADD.S rd, rs1, rs2

Floating-point arithmetic instructions with one or two source operands use the R-type format with the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of rs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd.

ISA: f

", "tooltip": "Floating-point arithmetic instructions with one or two source operands use the R-type format with the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of rs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd.\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#sec:single-float-compute" }; case "FCLASS.D": return { "html": "

FCLASS.D rd, rs1

The double-precision floating-point classify instruction, FCLASS.D, is defined analogously to its single-precision counterpart, but operates on double-precision operands.

ISA: d

", "tooltip": "The double-precision floating-point classify instruction, FCLASS.D, is defined analogously to its single-precision counterpart, but operates on double-precision operands.\n\n\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/d.html#double-precision-floating-point-classify-instruction" }; case "FCLASS.H": return { "html": "

FCLASS.H rd, rs1

The half-precision floating-point classify instruction, FCLASS.H, is defined analogously to its single-precision counterpart, but operates on half-precision operands.

ISA: zfh

", "tooltip": "The half-precision floating-point classify instruction, FCLASS.H, is defined analogously to its single-precision counterpart, but operates on half-precision operands.\n\n\n\n(ISA: zfh)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/zfh.html#half-precision-floating-point-classify-instruction" }; case "FCLASS.Q": return { "html": "

FCLASS.Q rd, rs1

The quad-precision floating-point classify instruction, FCLASS.Q, is defined analogously to its double-precision counterpart, but operates on quad-precision operands.

ISA: q

", "tooltip": "The quad-precision floating-point classify instruction, FCLASS.Q, is defined analogously to its double-precision counterpart, but operates on quad-precision operands.\n\n\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/q.html#quad-precision-floating-point-classify-instruction" }; case "FCLASS.S": return { "html": "

FCLASS.S rd, rs1

The FCLASS.S instruction examines the value in floating-point register rs1 and writes to integer register rd a 10-bit mask that indicates the class of the floating-point number. The format of the mask is described in Table [tab:fclass] . The corresponding bit in rd will be set if the property is true and clear otherwise. All other bits in rd are cleared. Note that exactly one bit in rd will be set. FCLASS.S does not set the floating-point exception flags.

ISA: f

", "tooltip": "The FCLASS.S instruction examines the value in floating-point register rs1 and writes to integer register rd a 10-bit mask that indicates the class of the floating-point number. The format of the mask is described in Table [tab:fclass] . The corresponding bit in rd will be set if the property is true and clear otherwise. All other bits in rd are cleared. Note that exactly one bit in rd will be set. FCLASS.S does not set the floating-point exception flags.\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-floating-point-classify-instruction" }; case "FCVT.D.H": return { "html": "

FCVT.D.H rd, rs1

New floating-point-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision floating-point-to-floating-point conversion instructions. FCVT.S.H or FCVT.H.S converts a half-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively. If the D extension is present, FCVT.D.H or FCVT.H.D converts a half-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively. If the Q extension is present, FCVT.Q.H or FCVT.H.Q converts a half-precision floating-point number to a quad-precision floating-point number, or vice-versa, respectively.

ISA: zfh

", "tooltip": "New floating-point-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision floating-point-to-floating-point conversion instructions. FCVT.S.H or FCVT.H.S converts a half-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively. If the D extension is present, FCVT.D.H or FCVT.H.D converts a half-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively. If the Q extension is present, FCVT.Q.H or FCVT.H.Q converts a half-precision floating-point number to a quad-precision floating-point number, or vice-versa, respectively.\n\n\n\n(ISA: zfh)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/zfh.html#half-precision-convert-and-move-instructions" }; case "FCVT.D.L": return { "html": "

FCVT.D.L rd, rs1

Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.D or FCVT.L.D converts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.D.W or FCVT.D.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a double-precision floating-point number in floating-point register rd. FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values. For RV64, FCVT.W[U].D sign-extends the 32-bit result. FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions. The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S.

ISA: d

", "tooltip": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.D or FCVT.L.D converts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.D.W or FCVT.D.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a double-precision floating-point number in floating-point register rd. FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values. For RV64, FCVT.W[U].D sign-extends the 32-bit result. FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions. The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S.\n\n\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/d.html#double-precision-floating-point-conversion-and-move-instructions" }; case "FCVT.D.LU": return { "html": "

FCVT.D.LU rd, rs1

Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.D or FCVT.L.D converts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.D.W or FCVT.D.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a double-precision floating-point number in floating-point register rd. FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values. For RV64, FCVT.W[U].D sign-extends the 32-bit result. FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions. The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S.

ISA: d

FCVT.D.Q rd, rs1

New floating-point-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision floating-point-to-floating-point conversion instructions. FCVT.S.Q or FCVT.Q.S converts a quad-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively. FCVT.D.Q or FCVT.Q.D converts a quad-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively.

ISA: q

", "tooltip": "New floating-point-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision floating-point-to-floating-point conversion instructions. FCVT.S.Q or FCVT.Q.S converts a quad-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively. FCVT.D.Q or FCVT.Q.D converts a quad-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively.\n\n\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/q.html#quad-precision-convert-and-move-instructions" }; case "FCVT.D.S": return { "html": "

FCVT.D.S rd, rs1

The double-precision to single-precision and single-precision to double-precision conversion instructions, FCVT.S.D and FCVT.D.S, are encoded in the OP-FP major opcode space and both the source and destination are floating-point registers. The rs2 field encodes the datatype of the source, and the fmt field encodes the datatype of the destination. FCVT.S.D rounds according to the RM field; FCVT.D.S will never round.

ISA: d

", "tooltip": "The double-precision to single-precision and single-precision to double-precision conversion instructions, FCVT.S.D and FCVT.D.S, are encoded in the OP-FP major opcode space and both the source and destination are floating-point registers. The rs2 field encodes the datatype of the source, and the fmt field encodes the datatype of the destination. FCVT.S.D rounds according to the RM field; FCVT.D.S will never round.\n\n\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/d.html#double-precision-floating-point-conversion-and-move-instructions" }; case "FCVT.D.W": return { "html": "

FCVT.D.W rd, rs1

Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.D or FCVT.L.D converts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.D.W or FCVT.D.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a double-precision floating-point number in floating-point register rd. FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values. For RV64, FCVT.W[U].D sign-extends the 32-bit result. FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions. The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S.
All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. Note FCVT.D.W[U] always produces an exact result and is unaffected by rounding mode.

ISA: d

", "tooltip": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.D or FCVT.L.D converts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.D.W or FCVT.D.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a double-precision floating-point number in floating-point register rd. FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values. For RV64, FCVT.W[U].D sign-extends the 32-bit result. FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions. The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S.\nAll floating-point to integer and integer to floating-point conversion instructions round according to the rm field. Note FCVT.D.W[U] always produces an exact result and is unaffected by rounding mode.\n\n\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/d.html#double-precision-floating-point-conversion-and-move-instructions" }; case "FCVT.D.WU": return { "html": "

FCVT.D.WU rd, rs1

Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.D or FCVT.L.D converts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.D.W or FCVT.D.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a double-precision floating-point number in floating-point register rd. FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values. For RV64, FCVT.W[U].D sign-extends the 32-bit result. FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions. The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S.

ISA: d

FCVT.H.D rd, rs1

New floating-point-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision floating-point-to-floating-point conversion instructions. FCVT.S.H or FCVT.H.S converts a half-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively. If the D extension is present, FCVT.D.H or FCVT.H.D converts a half-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively. If the Q extension is present, FCVT.Q.H or FCVT.H.Q converts a half-precision floating-point number to a quad-precision floating-point number, or vice-versa, respectively.

ISA: zfh

FCVT.H.L rd, rs1

New floating-point-to-integer and integer-to-floating-point conversion instructions are added. These instructions are defined analogously to the single-precision-to-integer and integer-to-single-precision conversion instructions. FCVT.W.H or FCVT.L.H converts a half-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.H.W or FCVT.H.L converts a 32-bit or 64-bit signed integer, respectively, into a half-precision floating-point number. FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions.

ISA: zfh

", "tooltip": "New floating-point-to-integer and integer-to-floating-point conversion instructions are added. These instructions are defined analogously to the single-precision-to-integer and integer-to-single-precision conversion instructions. FCVT.W.H or FCVT.L.H converts a half-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.H.W or FCVT.H.L converts a 32-bit or 64-bit signed integer, respectively, into a half-precision floating-point number. FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions.\n\n\n\n(ISA: zfh)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/zfh.html#half-precision-convert-and-move-instructions" }; case "FCVT.H.LU": return { "html": "

FCVT.H.LU rd, rs1

New floating-point-to-integer and integer-to-floating-point conversion instructions are added. These instructions are defined analogously to the single-precision-to-integer and integer-to-single-precision conversion instructions. FCVT.W.H or FCVT.L.H converts a half-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.H.W or FCVT.H.L converts a 32-bit or 64-bit signed integer, respectively, into a half-precision floating-point number. FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions.

ISA: zfh

FCVT.H.Q rd, rs1

New floating-point-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision floating-point-to-floating-point conversion instructions. FCVT.S.H or FCVT.H.S converts a half-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively. If the D extension is present, FCVT.D.H or FCVT.H.D converts a half-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively. If the Q extension is present, FCVT.Q.H or FCVT.H.Q converts a half-precision floating-point number to a quad-precision floating-point number, or vice-versa, respectively.

ISA: zfh

FCVT.H.S rd, rs1

New floating-point-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision floating-point-to-floating-point conversion instructions. FCVT.S.H or FCVT.H.S converts a half-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively. If the D extension is present, FCVT.D.H or FCVT.H.D converts a half-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively. If the Q extension is present, FCVT.Q.H or FCVT.H.Q converts a half-precision floating-point number to a quad-precision floating-point number, or vice-versa, respectively.

ISA: zfh

FCVT.H.W rd, rs1

New floating-point-to-integer and integer-to-floating-point conversion instructions are added. These instructions are defined analogously to the single-precision-to-integer and integer-to-single-precision conversion instructions. FCVT.W.H or FCVT.L.H converts a half-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.H.W or FCVT.H.L converts a 32-bit or 64-bit signed integer, respectively, into a half-precision floating-point number. FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions.

ISA: zfh

FCVT.H.WU rd, rs1

New floating-point-to-integer and integer-to-floating-point conversion instructions are added. These instructions are defined analogously to the single-precision-to-integer and integer-to-single-precision conversion instructions. FCVT.W.H or FCVT.L.H converts a half-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.H.W or FCVT.H.L converts a 32-bit or 64-bit signed integer, respectively, into a half-precision floating-point number. FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions.

ISA: zfh

FCVT.L.D rd, rs1

Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.D or FCVT.L.D converts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.D.W or FCVT.D.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a double-precision floating-point number in floating-point register rd. FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values. For RV64, FCVT.W[U].D sign-extends the 32-bit result. FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions. The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S.

ISA: d

FCVT.L.H rd, rs1

New floating-point-to-integer and integer-to-floating-point conversion instructions are added. These instructions are defined analogously to the single-precision-to-integer and integer-to-single-precision conversion instructions. FCVT.W.H or FCVT.L.H converts a half-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.H.W or FCVT.H.L converts a 32-bit or 64-bit signed integer, respectively, into a half-precision floating-point number. FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions.

ISA: zfh

FCVT.L.Q rd, rs1

New floating-point-to-integer and integer-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision-to-integer and integer-to-double-precision conversion instructions. FCVT.W.Q or FCVT.L.Q converts a quad-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.Q.W or FCVT.Q.L converts a 32-bit or 64-bit signed integer, respectively, into a quad-precision floating-point number. FCVT.WU.Q, FCVT.LU.Q, FCVT.Q.WU, and FCVT.Q.LU variants convert to or from unsigned integer values. FCVT.L[U].Q and FCVT.Q.L[U] are RV64-only instructions.

ISA: q

", "tooltip": "New floating-point-to-integer and integer-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision-to-integer and integer-to-double-precision conversion instructions. FCVT.W.Q or FCVT.L.Q converts a quad-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.Q.W or FCVT.Q.L converts a 32-bit or 64-bit signed integer, respectively, into a quad-precision floating-point number. FCVT.WU.Q, FCVT.LU.Q, FCVT.Q.WU, and FCVT.Q.LU variants convert to or from unsigned integer values. FCVT.L[U].Q and FCVT.Q.L[U] are RV64-only instructions.\n\n\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/q.html#quad-precision-convert-and-move-instructions" }; case "FCVT.L.S": return { "html": "

FCVT.L.S rd, rs1

Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN > 32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set. Table [tab:int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs.
FCVT.L.S

ISA: f

", "tooltip": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN > 32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set. Table [tab:int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs.\nFCVT.L.S\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-floating-point-conversion-and-move-instructions" }; case "FCVT.LU.D": return { "html": "

FCVT.LU.D rd, rs1

Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.D or FCVT.L.D converts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.D.W or FCVT.D.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a double-precision floating-point number in floating-point register rd. FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values. For RV64, FCVT.W[U].D sign-extends the 32-bit result. FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions. The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S.

ISA: d

FCVT.LU.H rd, rs1

New floating-point-to-integer and integer-to-floating-point conversion instructions are added. These instructions are defined analogously to the single-precision-to-integer and integer-to-single-precision conversion instructions. FCVT.W.H or FCVT.L.H converts a half-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.H.W or FCVT.H.L converts a 32-bit or 64-bit signed integer, respectively, into a half-precision floating-point number. FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions.

ISA: zfh

FCVT.LU.Q rd, rs1

New floating-point-to-integer and integer-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision-to-integer and integer-to-double-precision conversion instructions. FCVT.W.Q or FCVT.L.Q converts a quad-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.Q.W or FCVT.Q.L converts a 32-bit or 64-bit signed integer, respectively, into a quad-precision floating-point number. FCVT.WU.Q, FCVT.LU.Q, FCVT.Q.WU, and FCVT.Q.LU variants convert to or from unsigned integer values. FCVT.L[U].Q and FCVT.Q.L[U] are RV64-only instructions.

ISA: q

FCVT.LU.S rd, rs1

Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN > 32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set. Table [tab:int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs.
FCVT.LU.S

ISA: f

", "tooltip": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN > 32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set. Table [tab:int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs.\nFCVT.LU.S\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-floating-point-conversion-and-move-instructions" }; case "FCVT.Q.D": return { "html": "

FCVT.Q.D rd, rs1

New floating-point-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision floating-point-to-floating-point conversion instructions. FCVT.S.Q or FCVT.Q.S converts a quad-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively. FCVT.D.Q or FCVT.Q.D converts a quad-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively.

ISA: q

", "tooltip": "New floating-point-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision floating-point-to-floating-point conversion instructions. FCVT.S.Q or FCVT.Q.S converts a quad-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively. FCVT.D.Q or FCVT.Q.D converts a quad-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively.\n\n\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/q.html#quad-precision-convert-and-move-instructions" }; case "FCVT.Q.H": return { "html": "

FCVT.Q.H rd, rs1

New floating-point-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision floating-point-to-floating-point conversion instructions. FCVT.S.H or FCVT.H.S converts a half-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively. If the D extension is present, FCVT.D.H or FCVT.H.D converts a half-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively. If the Q extension is present, FCVT.Q.H or FCVT.H.Q converts a half-precision floating-point number to a quad-precision floating-point number, or vice-versa, respectively.

ISA: zfh

FCVT.Q.L rd, rs1

New floating-point-to-integer and integer-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision-to-integer and integer-to-double-precision conversion instructions. FCVT.W.Q or FCVT.L.Q converts a quad-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.Q.W or FCVT.Q.L converts a 32-bit or 64-bit signed integer, respectively, into a quad-precision floating-point number. FCVT.WU.Q, FCVT.LU.Q, FCVT.Q.WU, and FCVT.Q.LU variants convert to or from unsigned integer values. FCVT.L[U].Q and FCVT.Q.L[U] are RV64-only instructions.

ISA: q

FCVT.Q.LU rd, rs1

New floating-point-to-integer and integer-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision-to-integer and integer-to-double-precision conversion instructions. FCVT.W.Q or FCVT.L.Q converts a quad-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.Q.W or FCVT.Q.L converts a 32-bit or 64-bit signed integer, respectively, into a quad-precision floating-point number. FCVT.WU.Q, FCVT.LU.Q, FCVT.Q.WU, and FCVT.Q.LU variants convert to or from unsigned integer values. FCVT.L[U].Q and FCVT.Q.L[U] are RV64-only instructions.

ISA: q

FCVT.Q.S rd, rs1

New floating-point-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision floating-point-to-floating-point conversion instructions. FCVT.S.Q or FCVT.Q.S converts a quad-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively. FCVT.D.Q or FCVT.Q.D converts a quad-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively.

ISA: q

", "tooltip": "New floating-point-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision floating-point-to-floating-point conversion instructions. FCVT.S.Q or FCVT.Q.S converts a quad-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively. FCVT.D.Q or FCVT.Q.D converts a quad-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively.\n\n\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/q.html#quad-precision-convert-and-move-instructions" }; case "FCVT.Q.W": return { "html": "

FCVT.Q.W rd, rs1

New floating-point-to-integer and integer-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision-to-integer and integer-to-double-precision conversion instructions. FCVT.W.Q or FCVT.L.Q converts a quad-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.Q.W or FCVT.Q.L converts a 32-bit or 64-bit signed integer, respectively, into a quad-precision floating-point number. FCVT.WU.Q, FCVT.LU.Q, FCVT.Q.WU, and FCVT.Q.LU variants convert to or from unsigned integer values. FCVT.L[U].Q and FCVT.Q.L[U] are RV64-only instructions.

ISA: q

FCVT.Q.WU rd, rs1

New floating-point-to-integer and integer-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision-to-integer and integer-to-double-precision conversion instructions. FCVT.W.Q or FCVT.L.Q converts a quad-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.Q.W or FCVT.Q.L converts a 32-bit or 64-bit signed integer, respectively, into a quad-precision floating-point number. FCVT.WU.Q, FCVT.LU.Q, FCVT.Q.WU, and FCVT.Q.LU variants convert to or from unsigned integer values. FCVT.L[U].Q and FCVT.Q.L[U] are RV64-only instructions.

ISA: q

FCVT.S.D rd, rs1

The double-precision to single-precision and single-precision to double-precision conversion instructions, FCVT.S.D and FCVT.D.S, are encoded in the OP-FP major opcode space and both the source and destination are floating-point registers. The rs2 field encodes the datatype of the source, and the fmt field encodes the datatype of the destination. FCVT.S.D rounds according to the RM field; FCVT.D.S will never round.

ISA: d

FCVT.S.H rd, rs1

New floating-point-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision floating-point-to-floating-point conversion instructions. FCVT.S.H or FCVT.H.S converts a half-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively. If the D extension is present, FCVT.D.H or FCVT.H.D converts a half-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively. If the Q extension is present, FCVT.Q.H or FCVT.H.Q converts a half-precision floating-point number to a quad-precision floating-point number, or vice-versa, respectively.

ISA: zfh

FCVT.S.L rd, rs1

Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN > 32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set. Table [tab:int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs.

ISA: f

", "tooltip": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN > 32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set. Table [tab:int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs.\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-floating-point-conversion-and-move-instructions" }; case "FCVT.S.LU": return { "html": "

FCVT.S.LU rd, rs1

Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN > 32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set. Table [tab:int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs.

ISA: f

", "tooltip": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN > 32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set. Table [tab:int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs.\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-floating-point-conversion-and-move-instructions" }; case "FCVT.S.Q": return { "html": "

FCVT.S.Q rd, rs1

New floating-point-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision floating-point-to-floating-point conversion instructions. FCVT.S.Q or FCVT.Q.S converts a quad-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively. FCVT.D.Q or FCVT.Q.D converts a quad-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively.

ISA: q

", "tooltip": "New floating-point-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision floating-point-to-floating-point conversion instructions. FCVT.S.Q or FCVT.Q.S converts a quad-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively. FCVT.D.Q or FCVT.Q.D converts a quad-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively.\n\n\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/q.html#quad-precision-convert-and-move-instructions" }; case "FCVT.S.W": return { "html": "

FCVT.S.W rd, rs1

Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN > 32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set. Table [tab:int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs.
All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags.

ISA: f

", "tooltip": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN > 32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set. Table [tab:int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs.\nAll floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags.\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-floating-point-conversion-and-move-instructions" }; case "FCVT.S.WU": return { "html": "

FCVT.S.WU rd, rs1

Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN > 32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set. Table [tab:int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs.

ISA: f

", "tooltip": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN > 32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set. Table [tab:int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs.\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-floating-point-conversion-and-move-instructions" }; case "FCVT.W.D": return { "html": "

FCVT.W.D rd, rs1

Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.D or FCVT.L.D converts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.D.W or FCVT.D.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a double-precision floating-point number in floating-point register rd. FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values. For RV64, FCVT.W[U].D sign-extends the 32-bit result. FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions. The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S.

ISA: d

FCVT.W.H rd, rs1

New floating-point-to-integer and integer-to-floating-point conversion instructions are added. These instructions are defined analogously to the single-precision-to-integer and integer-to-single-precision conversion instructions. FCVT.W.H or FCVT.L.H converts a half-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.H.W or FCVT.H.L converts a 32-bit or 64-bit signed integer, respectively, into a half-precision floating-point number. FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions.

ISA: zfh

FCVT.W.Q rd, rs1

New floating-point-to-integer and integer-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision-to-integer and integer-to-double-precision conversion instructions. FCVT.W.Q or FCVT.L.Q converts a quad-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.Q.W or FCVT.Q.L converts a 32-bit or 64-bit signed integer, respectively, into a quad-precision floating-point number. FCVT.WU.Q, FCVT.LU.Q, FCVT.Q.WU, and FCVT.Q.LU variants convert to or from unsigned integer values. FCVT.L[U].Q and FCVT.Q.L[U] are RV64-only instructions.

ISA: q

FCVT.W.S rd, rs1

Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN > 32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set. Table [tab:int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs.
FCVT.W.S

ISA: f

", "tooltip": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN > 32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set. Table [tab:int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs.\nFCVT.W.S\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-floating-point-conversion-and-move-instructions" }; case "FCVT.WU.D": return { "html": "

FCVT.WU.D rd, rs1

Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.D or FCVT.L.D converts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.D.W or FCVT.D.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a double-precision floating-point number in floating-point register rd. FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values. For RV64, FCVT.W[U].D sign-extends the 32-bit result. FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions. The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S.

ISA: d

FCVT.WU.H rd, rs1

New floating-point-to-integer and integer-to-floating-point conversion instructions are added. These instructions are defined analogously to the single-precision-to-integer and integer-to-single-precision conversion instructions. FCVT.W.H or FCVT.L.H converts a half-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.H.W or FCVT.H.L converts a 32-bit or 64-bit signed integer, respectively, into a half-precision floating-point number. FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions.

ISA: zfh

FCVT.WU.Q rd, rs1

New floating-point-to-integer and integer-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision-to-integer and integer-to-double-precision conversion instructions. FCVT.W.Q or FCVT.L.Q converts a quad-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.Q.W or FCVT.Q.L converts a 32-bit or 64-bit signed integer, respectively, into a quad-precision floating-point number. FCVT.WU.Q, FCVT.LU.Q, FCVT.Q.WU, and FCVT.Q.LU variants convert to or from unsigned integer values. FCVT.L[U].Q and FCVT.Q.L[U] are RV64-only instructions.

ISA: q

FCVT.WU.S rd, rs1

Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN > 32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set. Table [tab:int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs.
FCVT.WU.S

ISA: f

", "tooltip": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN > 32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set. Table [tab:int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs.\nFCVT.WU.S\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-floating-point-conversion-and-move-instructions" }; case "FDIV.D": return { "html": "

FDIV.D rd, rs1, rs2

ISA: d

", "tooltip": "\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FDIV.H": return { "html": "

FDIV.H rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FDIV.Q": return { "html": "

FDIV.Q rd, rs1, rs2

ISA: q

", "tooltip": "\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FDIV.S": return { "html": "

FDIV.S rd, rs1, rs2

Floating-point arithmetic instructions with one or two source operands use the R-type format with the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of rs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd.

ISA: f

FENCE rs1, rd

RV32I was designed to be sufficient to form a compiler target and to support modern operating system environments. The ISA was also designed to reduce the hardware required in a minimal implementation. RV32I contains 40 unique instructions, though a simple implementation might cover the ECALL/EBREAK instructions with a single SYSTEM hardware instruction that always traps and might be able to implement the FENCE instruction as a NOP, reducing base instruction count to 38 total. RV32I can emulate almost any other ISA extension (except the A extension, which requires additional hardware support for atomicity).

ISA: rv32

FENCE.I imm12, rs1, rd

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FENCE.TSO": return { "html": "

FENCE.TSO rs1, rd

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FEQ.D": return { "html": "

FEQ.D rd, rs1, rs2

ISA: d

", "tooltip": "\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FEQ.H": return { "html": "

FEQ.H rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FEQ.Q": return { "html": "

FEQ.Q rd, rs1, rs2

ISA: q

", "tooltip": "\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FEQ.S": return { "html": "

FEQ.S rd, rs1, rs2

Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 \\leq rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise.
FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons: that is, they set the invalid operation exception flag if either input is NaN. FEQ.S performs a quiet comparison: it only sets the invalid operation exception flag if either input is a signaling NaN. For all three instructions, the result is 0 if either operand is NaN.

ISA: f

", "tooltip": "Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 \\leq rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise.\nFLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons: that is, they set the invalid operation exception flag if either input is NaN. FEQ.S performs a quiet comparison: it only sets the invalid operation exception flag if either input is a signaling NaN. For all three instructions, the result is 0 if either operand is NaN.\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-floating-point-compare-instructions" }; case "FLD": return { "html": "

FLD rd, rs1, imm12

The FLD instruction loads a double-precision floating-point value from memory into floating-point register rd. FSD stores a double-precision value from the floating-point registers to memory.
FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN>=64.
FLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

ISA: d

", "tooltip": "The FLD instruction loads a double-precision floating-point value from memory into floating-point register rd. FSD stores a double-precision value from the floating-point registers to memory.\nFLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN>=64.\nFLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.\n\n\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/d.html#fld_fsd" }; case "FLE.D": return { "html": "

FLE.D rd, rs1, rs2

ISA: d

", "tooltip": "\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FLE.H": return { "html": "

FLE.H rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FLE.Q": return { "html": "

FLE.Q rd, rs1, rs2

ISA: q

", "tooltip": "\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FLE.S": return { "html": "

FLE.S rd, rs1, rs2

Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 \\leq rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise.
FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons: that is, they set the invalid operation exception flag if either input is NaN. FEQ.S performs a quiet comparison: it only sets the invalid operation exception flag if either input is a signaling NaN. For all three instructions, the result is 0 if either operand is NaN.

ISA: f

FLH rd, rs1, imm12

FLH and FSH are only guaranteed to execute atomically if the effective address is naturally aligned.
FLH and FSH do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. FLH NaN-boxes the result written to rd, whereas FSH ignores all but the lower 16 bits in rs2.

ISA: zfh

", "tooltip": "FLH and FSH are only guaranteed to execute atomically if the effective address is naturally aligned.\nFLH and FSH do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. FLH NaN-boxes the result written to rd, whereas FSH ignores all but the lower 16 bits in rs2.\n\n\n\n(ISA: zfh)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/zfh.html#half-precision-load-and-store-instructions" }; case "FLQ": return { "html": "

FLQ rd, rs1, imm12

FLQ and FSQ are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN=128.
FLQ and FSQ do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

ISA: q

", "tooltip": "FLQ and FSQ are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN=128.\nFLQ and FSQ do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.\n\n\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/q.html#quad-precision-load-and-store-instructions" }; case "FLT.D": return { "html": "

FLT.D rd, rs1, rs2

ISA: d

", "tooltip": "\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FLT.H": return { "html": "

FLT.H rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FLT.Q": return { "html": "

FLT.Q rd, rs1, rs2

ISA: q

", "tooltip": "\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FLT.S": return { "html": "

FLT.S rd, rs1, rs2

Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 \\leq rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise.
FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons: that is, they set the invalid operation exception flag if either input is NaN. FEQ.S performs a quiet comparison: it only sets the invalid operation exception flag if either input is a signaling NaN. For all three instructions, the result is 0 if either operand is NaN.

ISA: f

FLW rd, rs1, imm12

Floating-point loads and stores use the same base+offset addressing mode as the integer base ISAs, with a base address in register rs1 and a 12-bit signed byte offset. The FLW instruction loads a single-precision floating-point value from memory into floating-point register rd. FSW stores a single-precision value from floating-point register rs2 to memory.
FLW and FSW are only guaranteed to execute atomically if the effective address is naturally aligned.
FLW and FSW do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

ISA: f

", "tooltip": "Floating-point loads and stores use the same base+offset addressing mode as the integer base ISAs, with a base address in register rs1 and a 12-bit signed byte offset. The FLW instruction loads a single-precision floating-point value from memory into floating-point register rd. FSW stores a single-precision value from floating-point register rs2 to memory.\nFLW and FSW are only guaranteed to execute atomically if the effective address is naturally aligned.\nFLW and FSW do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-load-and-store-instructions" }; case "FMADD.D": return { "html": "

FMADD.D rd, rs1, rs2, rs3

ISA: d

", "tooltip": "\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FMADD.H": return { "html": "

FMADD.H rd, rs1, rs2, rs3

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FMADD.Q": return { "html": "

FMADD.Q rd, rs1, rs2, rs3

ISA: q

", "tooltip": "\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FMADD.S": return { "html": "

FMADD.S rd, rs1, rs2, rs3

FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to rd. FMADD.S computes (rs1\u00d7rs2)+rs3.

ISA: f

", "tooltip": "FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to rd. FMADD.S computes (rs1\u00d7rs2)+rs3.\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#sec:single-float-compute" }; case "FMAX.D": return { "html": "

FMAX.D rd, rs1, rs2

ISA: d

", "tooltip": "\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FMAX.H": return { "html": "

FMAX.H rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FMAX.Q": return { "html": "

FMAX.Q rd, rs1, rs2

ISA: q

", "tooltip": "\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FMAX.S": return { "html": "

FMAX.S rd, rs1, rs2

Floating-point minimum-number and maximum-number instructions FMIN.S and FMAX.S write, respectively, the smaller or larger of rs1 and rs2 to rd. For the purposes of these instructions only, the value - 0.0 is considered to be less than the value + 0.0. If both inputs are NaNs, the result is the canonical NaN. If only one operand is a NaN, the result is the non-NaN operand. Signaling NaN inputs set the invalid operation exception flag, even when the result is not NaN.
Note that in version 2.2 of the F extension, the FMIN.S and FMAX.S instructions were amended to implement the proposed IEEE 754-201x minimumNumber and maximumNumber operations, rather than the IEEE 754-2008 minNum and maxNum operations. These operations differ in their handling of signaling NaNs.

ISA: f

", "tooltip": "Floating-point minimum-number and maximum-number instructions FMIN.S and FMAX.S write, respectively, the smaller or larger of rs1 and rs2 to rd. For the purposes of these instructions only, the value - 0.0 is considered to be less than the value + 0.0. If both inputs are NaNs, the result is the canonical NaN. If only one operand is a NaN, the result is the non-NaN operand. Signaling NaN inputs set the invalid operation exception flag, even when the result is not NaN.\nNote that in version 2.2 of the F extension, the FMIN.S and FMAX.S instructions were amended to implement the proposed IEEE 754-201x minimumNumber and maximumNumber operations, rather than the IEEE 754-2008 minNum and maxNum operations. These operations differ in their handling of signaling NaNs.\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#sec:single-float-compute" }; case "FMIN.D": return { "html": "

FMIN.D rd, rs1, rs2

ISA: d

", "tooltip": "\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FMIN.H": return { "html": "

FMIN.H rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FMIN.Q": return { "html": "

FMIN.Q rd, rs1, rs2

ISA: q

", "tooltip": "\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FMIN.S": return { "html": "

FMIN.S rd, rs1, rs2

Floating-point minimum-number and maximum-number instructions FMIN.S and FMAX.S write, respectively, the smaller or larger of rs1 and rs2 to rd. For the purposes of these instructions only, the value - 0.0 is considered to be less than the value + 0.0. If both inputs are NaNs, the result is the canonical NaN. If only one operand is a NaN, the result is the non-NaN operand. Signaling NaN inputs set the invalid operation exception flag, even when the result is not NaN.
Note that in version 2.2 of the F extension, the FMIN.S and FMAX.S instructions were amended to implement the proposed IEEE 754-201x minimumNumber and maximumNumber operations, rather than the IEEE 754-2008 minNum and maxNum operations. These operations differ in their handling of signaling NaNs.

ISA: f

FMSUB.D rd, rs1, rs2, rs3

ISA: d

", "tooltip": "\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FMSUB.H": return { "html": "

FMSUB.H rd, rs1, rs2, rs3

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FMSUB.Q": return { "html": "

FMSUB.Q rd, rs1, rs2, rs3

ISA: q

", "tooltip": "\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FMSUB.S": return { "html": "

FMSUB.S rd, rs1, rs2, rs3

FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result to rd. FMSUB.S computes (rs1\u00d7rs2)-rs3.

ISA: f

", "tooltip": "FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result to rd. FMSUB.S computes (rs1\u00d7rs2)-rs3.\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#sec:single-float-compute" }; case "FMUL.D": return { "html": "

FMUL.D rd, rs1, rs2

ISA: d

", "tooltip": "\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FMUL.H": return { "html": "

FMUL.H rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FMUL.Q": return { "html": "

FMUL.Q rd, rs1, rs2

ISA: q

", "tooltip": "\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FMUL.S": return { "html": "

FMUL.S rd, rs1, rs2

Floating-point arithmetic instructions with one or two source operands use the R-type format with the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of rs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd.

ISA: f

FMV.D rd, rs

For XLEN>=64 only, instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.D moves the double-precision value in floating-point register rs1 to a representation in IEEE 754-2008 standard encoding in integer register rd. FMV.D.X moves the double-precision value encoded in IEEE 754-2008 standard encoding from the integer register rs1 to the floating-point register rd.
FMV.X.D and FMV.D.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

Equivalent ASM:

fsgnj.d rd, rs, rs

ISA: d(pseudo)

", "tooltip": "For XLEN>=64 only, instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.D moves the double-precision value in floating-point register rs1 to a representation in IEEE 754-2008 standard encoding in integer register rd. FMV.D.X moves the double-precision value encoded in IEEE 754-2008 standard encoding from the integer register rs1 to the floating-point register rd.\nFMV.X.D and FMV.D.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.\n\nEquivalent ASM:\n\nfsgnj.d rd, rs, rs\n\n(ISA: d(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/d.html#double-precision-floating-point-conversion-and-move-instructions" }; case "FMV.D.X": return { "html": "

FMV.D.X rd, rs1

ISA: d

", "tooltip": "\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FMV.H.X": return { "html": "

FMV.H.X rd, rs1

FMV.H.X moves the half-precision value encoded in IEEE 754-2008 standard encoding from the lower 16 bits of integer register rs1 to the floating-point register rd, NaN-boxing the result.
FMV.X.H and FMV.H.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

ISA: zfh

", "tooltip": "FMV.H.X moves the half-precision value encoded in IEEE 754-2008 standard encoding from the lower 16 bits of integer register rs1 to the floating-point register rd, NaN-boxing the result.\nFMV.X.H and FMV.H.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.\n\n\n\n(ISA: zfh)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/zfh.html#half-precision-convert-and-move-instructions" }; case "FMV.S": return { "html": "

FMV.S rd, rs

Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S rx, ry, ry moves ry to rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the negation of ry to rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry moves the absolute value of ry to rx (assembler pseudoinstruction FABS.S rx, ry).
The FMV.W.X and FMV.X.W instructions were previously called FMV.S.X and FMV.X.S. The use of W is more consistent with their semantics as an instruction that moves 32 bits without interpreting them. This became clearer after defining NaN-boxing. To avoid disturbing existing code, both the W and S versions will be supported by tools.

Equivalent ASM:

fsgnj.s rd, rs, rs

ISA: f(pseudo)

", "tooltip": "Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S rx, ry, ry moves ry to rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the negation of ry to rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry moves the absolute value of ry to rx (assembler pseudoinstruction FABS.S rx, ry).\nThe FMV.W.X and FMV.X.W instructions were previously called FMV.S.X and FMV.X.S. The use of W is more consistent with their semantics as an instruction that moves 32 bits without interpreting them. This became clearer after defining NaN-boxing. To avoid disturbing existing code, both the W and S versions will be supported by tools.\n\nEquivalent ASM:\n\nfsgnj.s rd, rs, rs\n\n(ISA: f(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-floating-point-conversion-and-move-instructions" }; case "FMV.S.X": return { "html": "

FMV.S.X rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FMV.W.X": return { "html": "

FMV.W.X rd, rs1

FMV.W.X moves the single-precision value encoded in IEEE 754-2008 standard encoding from the lower 32 bits of integer register rs1 to the floating-point register rd. The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved.
The FMV.W.X and FMV.X.W instructions were previously called FMV.S.X and FMV.X.S. The use of W is more consistent with their semantics as an instruction that moves 32 bits without interpreting them. This became clearer after defining NaN-boxing. To avoid disturbing existing code, both the W and S versions will be supported by tools.

ISA: f

", "tooltip": "FMV.W.X moves the single-precision value encoded in IEEE 754-2008 standard encoding from the lower 32 bits of integer register rs1 to the floating-point register rd. The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved.\nThe FMV.W.X and FMV.X.W instructions were previously called FMV.S.X and FMV.X.S. The use of W is more consistent with their semantics as an instruction that moves 32 bits without interpreting them. This became clearer after defining NaN-boxing. To avoid disturbing existing code, both the W and S versions will be supported by tools.\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-floating-point-conversion-and-move-instructions" }; case "FMV.X.D": return { "html": "

FMV.X.D rd, rs1

For XLEN>=64 only, instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.D moves the double-precision value in floating-point register rs1 to a representation in IEEE 754-2008 standard encoding in integer register rd. FMV.D.X moves the double-precision value encoded in IEEE 754-2008 standard encoding from the integer register rs1 to the floating-point register rd.
FMV.X.D and FMV.D.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

ISA: d

", "tooltip": "For XLEN>=64 only, instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.D moves the double-precision value in floating-point register rs1 to a representation in IEEE 754-2008 standard encoding in integer register rd. FMV.D.X moves the double-precision value encoded in IEEE 754-2008 standard encoding from the integer register rs1 to the floating-point register rd.\nFMV.X.D and FMV.D.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.\n\n\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/d.html#double-precision-floating-point-conversion-and-move-instructions" }; case "FMV.X.H": return { "html": "

FMV.X.H rd, rs1

Instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.H moves the half-precision value in floating-point register rs1 to a representation in IEEE 754-2008 standard encoding in integer register rd, filling the upper XLEN-16 bits with copies of the floating-point number's sign bit.
FMV.X.H and FMV.H.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

ISA: zfh

", "tooltip": "Instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.H moves the half-precision value in floating-point register rs1 to a representation in IEEE 754-2008 standard encoding in integer register rd, filling the upper XLEN-16 bits with copies of the floating-point number's sign bit.\nFMV.X.H and FMV.H.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.\n\n\n\n(ISA: zfh)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/zfh.html#half-precision-convert-and-move-instructions" }; case "FMV.X.S": return { "html": "

FMV.X.S rd, rs1

The FMV.W.X and FMV.X.W instructions were previously called FMV.S.X and FMV.X.S. The use of W is more consistent with their semantics as an instruction that moves 32 bits without interpreting them. This became clearer after defining NaN-boxing. To avoid disturbing existing code, both the W and S versions will be supported by tools.

ISA: f

", "tooltip": "The FMV.W.X and FMV.X.W instructions were previously called FMV.S.X and FMV.X.S. The use of W is more consistent with their semantics as an instruction that moves 32 bits without interpreting them. This became clearer after defining NaN-boxing. To avoid disturbing existing code, both the W and S versions will be supported by tools.\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-floating-point-conversion-and-move-instructions" }; case "FMV.X.W": return { "html": "

FMV.X.W rd, rs1

Instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.W moves the single-precision value in floating-point register rs1 represented in IEEE 754-2008 encoding to the lower 32 bits of integer register rd. The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved. For RV64, the higher 32 bits of the destination register are filled with copies of the floating-point number's sign bit.
The FMV.W.X and FMV.X.W instructions were previously called FMV.S.X and FMV.X.S. The use of W is more consistent with their semantics as an instruction that moves 32 bits without interpreting them. This became clearer after defining NaN-boxing. To avoid disturbing existing code, both the W and S versions will be supported by tools.

ISA: f

", "tooltip": "Instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.W moves the single-precision value in floating-point register rs1 represented in IEEE 754-2008 encoding to the lower 32 bits of integer register rd. The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved. For RV64, the higher 32 bits of the destination register are filled with copies of the floating-point number's sign bit.\nThe FMV.W.X and FMV.X.W instructions were previously called FMV.S.X and FMV.X.S. The use of W is more consistent with their semantics as an instruction that moves 32 bits without interpreting them. This became clearer after defining NaN-boxing. To avoid disturbing existing code, both the W and S versions will be supported by tools.\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-floating-point-conversion-and-move-instructions" }; case "FNEG.D": return { "html": "

FNEG.D rd, rs

Equivalent ASM:

fsgnjn.d rd, rs, rs

ISA: d(pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\nfsgnjn.d rd, rs, rs\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FNEG.S": return { "html": "

FNEG.S rd, rs

Equivalent ASM:

fsgnjn.s rd, rs, rs

ISA: f(pseudo)

", "tooltip": "Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S rx, ry, ry moves ry to rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the negation of ry to rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry moves the absolute value of ry to rx (assembler pseudoinstruction FABS.S rx, ry).\n\nEquivalent ASM:\n\nfsgnjn.s rd, rs, rs\n\n(ISA: f(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-floating-point-conversion-and-move-instructions" }; case "FNMADD.D": return { "html": "

FNMADD.D rd, rs1, rs2, rs3

ISA: d

", "tooltip": "\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FNMADD.H": return { "html": "

FNMADD.H rd, rs1, rs2, rs3

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FNMADD.Q": return { "html": "

FNMADD.Q rd, rs1, rs2, rs3

ISA: q

", "tooltip": "\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FNMADD.S": return { "html": "

FNMADD.S rd, rs1, rs2, rs3

FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, and writes the final result to rd. FNMADD.S computes -(rs1\u00d7rs2)-rs3.

ISA: f

", "tooltip": "FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, and writes the final result to rd. FNMADD.S computes -(rs1\u00d7rs2)-rs3.\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#sec:single-float-compute" }; case "FNMSUB.D": return { "html": "

FNMSUB.D rd, rs1, rs2, rs3

ISA: d

", "tooltip": "\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FNMSUB.H": return { "html": "

FNMSUB.H rd, rs1, rs2, rs3

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FNMSUB.Q": return { "html": "

FNMSUB.Q rd, rs1, rs2, rs3

ISA: q

", "tooltip": "\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FNMSUB.S": return { "html": "

FNMSUB.S rd, rs1, rs2, rs3

FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and writes the final result to rd. FNMSUB.S computes -(rs1\u00d7rs2)+rs3.

ISA: f

", "tooltip": "FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and writes the final result to rd. FNMSUB.S computes -(rs1\u00d7rs2)+rs3.\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#sec:single-float-compute" }; case "FRCSR": return { "html": "

FRCSR rd

The fcsr register can be read and written with the FRCSR and FSCSR instructions, which are assembler pseudoinstructions built on the underlying CSR access instructions. FRCSR reads fcsr by copying it into integer register rd. FSCSR swaps the value in fcsr by copying the original value into integer register rd, and then writing a new value obtained from integer register rs1 into fcsr.

ISA: f

", "tooltip": "The fcsr register can be read and written with the FRCSR and FSCSR instructions, which are assembler pseudoinstructions built on the underlying CSR access instructions. FRCSR reads fcsr by copying it into integer register rd. FSCSR swaps the value in fcsr by copying the original value into integer register rd, and then writing a new value obtained from integer register rs1 into fcsr.\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#floating-point-control-and-status-register" }; case "FRFLAGS": return { "html": "

FRFLAGS rd

The fields within the fcsr can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field frm and copies it into the least-significant three bits of integer register rd, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register rd, and then writing a new value obtained from the three least-significant bits of integer register rs1 into frm. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field fflags.

ISA: f

", "tooltip": "The fields within the fcsr can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field frm and copies it into the least-significant three bits of integer register rd, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register rd, and then writing a new value obtained from the three least-significant bits of integer register rs1 into frm. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field fflags.\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#floating-point-control-and-status-register" }; case "FRRM": return { "html": "

FRRM rd

The fields within the fcsr can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field frm and copies it into the least-significant three bits of integer register rd, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register rd, and then writing a new value obtained from the three least-significant bits of integer register rs1 into frm. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field fflags.

ISA: f

FSCSR rd, rs1

The fcsr register can be read and written with the FRCSR and FSCSR instructions, which are assembler pseudoinstructions built on the underlying CSR access instructions. FRCSR reads fcsr by copying it into integer register rd. FSCSR swaps the value in fcsr by copying the original value into integer register rd, and then writing a new value obtained from integer register rs1 into fcsr.

ISA: f

FSD rs1, rs2, imm12

The FLD instruction loads a double-precision floating-point value from memory into floating-point register rd. FSD stores a double-precision value from the floating-point registers to memory.
FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN>=64.
FLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

ISA: d

FSFLAGS rd, rs1

The fields within the fcsr can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field frm and copies it into the least-significant three bits of integer register rd, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register rd, and then writing a new value obtained from the three least-significant bits of integer register rs1 into frm. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field fflags.

ISA: f

FSFLAGSI rd, zimm

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FSGNJ.D": return { "html": "

FSGNJ.D rd, rs1, rs2

Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction.

ISA: d

", "tooltip": "Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction.\n\n\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/d.html#double-precision-floating-point-conversion-and-move-instructions" }; case "FSGNJ.H": return { "html": "

FSGNJ.H rd, rs1, rs2

Floating-point to floating-point sign-injection instructions, FSGNJ.H, FSGNJN.H, and FSGNJX.H are defined analogously to the single-precision sign-injection instruction.

ISA: zfh

", "tooltip": "Floating-point to floating-point sign-injection instructions, FSGNJ.H, FSGNJN.H, and FSGNJX.H are defined analogously to the single-precision sign-injection instruction.\n\n\n\n(ISA: zfh)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/zfh.html#half-precision-convert-and-move-instructions" }; case "FSGNJ.Q": return { "html": "

FSGNJ.Q rd, rs1, rs2

Floating-point to floating-point sign-injection instructions, FSGNJ.Q, FSGNJN.Q, and FSGNJX.Q are defined analogously to the double-precision sign-injection instruction.

ISA: q

", "tooltip": "Floating-point to floating-point sign-injection instructions, FSGNJ.Q, FSGNJN.Q, and FSGNJX.Q are defined analogously to the double-precision sign-injection instruction.\n\n\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/q.html#quad-precision-convert-and-move-instructions" }; case "FSGNJ.S": return { "html": "

FSGNJ.S rd, rs1, rs2

Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S rx, ry, ry moves ry to rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the negation of ry to rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry moves the absolute value of ry to rx (assembler pseudoinstruction FABS.S rx, ry).

ISA: f

", "tooltip": "Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S rx, ry, ry moves ry to rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the negation of ry to rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry moves the absolute value of ry to rx (assembler pseudoinstruction FABS.S rx, ry).\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-floating-point-conversion-and-move-instructions" }; case "FSGNJN.D": return { "html": "

FSGNJN.D rd, rs1, rs2

Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction.

ISA: d

FSGNJN.H rd, rs1, rs2

Floating-point to floating-point sign-injection instructions, FSGNJ.H, FSGNJN.H, and FSGNJX.H are defined analogously to the single-precision sign-injection instruction.

ISA: zfh

FSGNJN.Q rd, rs1, rs2

Floating-point to floating-point sign-injection instructions, FSGNJ.Q, FSGNJN.Q, and FSGNJX.Q are defined analogously to the double-precision sign-injection instruction.

ISA: q

FSGNJN.S rd, rs1, rs2

Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S rx, ry, ry moves ry to rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the negation of ry to rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry moves the absolute value of ry to rx (assembler pseudoinstruction FABS.S rx, ry).

ISA: f

", "tooltip": "Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S rx, ry, ry moves ry to rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the negation of ry to rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry moves the absolute value of ry to rx (assembler pseudoinstruction FABS.S rx, ry).\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-floating-point-conversion-and-move-instructions" }; case "FSGNJX.D": return { "html": "

FSGNJX.D rd, rs1, rs2

Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction.

ISA: d

FSGNJX.H rd, rs1, rs2

Floating-point to floating-point sign-injection instructions, FSGNJ.H, FSGNJN.H, and FSGNJX.H are defined analogously to the single-precision sign-injection instruction.

ISA: zfh

FSGNJX.Q rd, rs1, rs2

Floating-point to floating-point sign-injection instructions, FSGNJ.Q, FSGNJN.Q, and FSGNJX.Q are defined analogously to the double-precision sign-injection instruction.

ISA: q

FSGNJX.S rd, rs1, rs2

Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S rx, ry, ry moves ry to rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the negation of ry to rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry moves the absolute value of ry to rx (assembler pseudoinstruction FABS.S rx, ry).

ISA: f

", "tooltip": "Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S rx, ry, ry moves ry to rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the negation of ry to rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry moves the absolute value of ry to rx (assembler pseudoinstruction FABS.S rx, ry).\n\n\n\n(ISA: f)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-floating-point-conversion-and-move-instructions" }; case "FSH": return { "html": "

FSH rs1, rs2, imm12

FLH and FSH are only guaranteed to execute atomically if the effective address is naturally aligned.
FLH and FSH do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. FLH NaN-boxes the result written to rd, whereas FSH ignores all but the lower 16 bits in rs2.

ISA: zfh

FSQ rs1, rs2, imm12

FLQ and FSQ are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN=128.
FLQ and FSQ do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

ISA: q

FSQRT.D rd, rs1

ISA: d

", "tooltip": "\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FSQRT.H": return { "html": "

FSQRT.H rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FSQRT.Q": return { "html": "

FSQRT.Q rd, rs1

ISA: q

", "tooltip": "\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FSQRT.S": return { "html": "

FSQRT.S rd, rs1

Floating-point arithmetic instructions with one or two source operands use the R-type format with the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of rs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd.

ISA: f

FSRM rd, rs1

The fields within the fcsr can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field frm and copies it into the least-significant three bits of integer register rd, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register rd, and then writing a new value obtained from the three least-significant bits of integer register rs1 into frm. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field fflags.

ISA: f

FSRMI rd, zimm

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FSUB.D": return { "html": "

FSUB.D rd, rs1, rs2

ISA: d

", "tooltip": "\n\n(ISA: d)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FSUB.H": return { "html": "

FSUB.H rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FSUB.Q": return { "html": "

FSUB.Q rd, rs1, rs2

ISA: q

", "tooltip": "\n\n(ISA: q)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "FSUB.S": return { "html": "

FSUB.S rd, rs1, rs2

Floating-point arithmetic instructions with one or two source operands use the R-type format with the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of rs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd.

ISA: f

FSW rs1, rs2, imm12

Floating-point loads and stores use the same base+offset addressing mode as the integer base ISAs, with a base address in register rs1 and a 12-bit signed byte offset. The FLW instruction loads a single-precision floating-point value from memory into floating-point register rd. FSW stores a single-precision value from floating-point register rs2 to memory.
FLW and FSW are only guaranteed to execute atomically if the effective address is naturally aligned.
FLW and FSW do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

ISA: f

HFENCE.GVMA rs1, rs2

The Svinval extension splits SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA instructions into finer-grained invalidation and ordering operations that can be more efficiently batched or pipelined on certain classes of high-performance implementation.
If the hypervisor extension is implemented, the Svinval extension also provides two additional instructions: HINVAL.VVMA and HINVAL.GVMA. These have the same semantics as SINVAL.VMA, except that they combine with SFENCE.W.INVAL and SFENCE.INVAL.IR to replace HFENCE.VVMA and HFENCE.GVMA, respectively, instead of SFENCE.VMA. In addition, HINVAL.GVMA uses VMIDs instead of ASIDs.
SINVAL.VMA, HINVAL.VVMA, and HINVAL.GVMA require the same permissions and raise the same exceptions as SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively. In particular, an attempt to execute any of these instructions in U-mode always raises an illegal instruction exception, and an attempt to execute SINVAL.VMA or HINVAL.GVMA in S-mode or HS-mode when mstatus.TVM=1 also raises an illegal instruction exception. An attempt to execute HINVAL.VVMA or HINVAL.GVMA in VS-mode or VU-mode, or to execute SINVAL.VMA in VU-mode, raises a virtual instruction exception. When hstatus.VTVM=1, an attempt to execute SINVAL.VMA in VS-mode also raises a virtual instruction exception.
High-performance implementations will be able to pipeline the address-translation cache invalidation operations, and will defer any pipeline stalls or other memory ordering enforcement until an SFENCE.W.INVAL, SFENCE.INVAL.IR, SFENCE.VMA, HFENCE.GVMA, or HFENCE.VVMA instruction is executed.
Simpler implementations may implement SINVAL.VMA, HINVAL.VVMA, and HINVAL.GVMA identically to SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively, while implementing SFENCE.W.INVAL and SFENCE.INVAL.IR instructions as no-ops.

ISA: supervisor

", "tooltip": "The Svinval extension splits SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA instructions into finer-grained invalidation and ordering operations that can be more efficiently batched or pipelined on certain classes of high-performance implementation.\nIf the hypervisor extension is implemented, the Svinval extension also provides two additional instructions: HINVAL.VVMA and HINVAL.GVMA. These have the same semantics as SINVAL.VMA, except that they combine with SFENCE.W.INVAL and SFENCE.INVAL.IR to replace HFENCE.VVMA and HFENCE.GVMA, respectively, instead of SFENCE.VMA. In addition, HINVAL.GVMA uses VMIDs instead of ASIDs.\nSINVAL.VMA, HINVAL.VVMA, and HINVAL.GVMA require the same permissions and raise the same exceptions as SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively. In particular, an attempt to execute any of these instructions in U-mode always raises an illegal instruction exception, and an attempt to execute SINVAL.VMA or HINVAL.GVMA in S-mode or HS-mode when mstatus.TVM=1 also raises an illegal instruction exception. An attempt to execute HINVAL.VVMA or HINVAL.GVMA in VS-mode or VU-mode, or to execute SINVAL.VMA in VU-mode, raises a virtual instruction exception. When hstatus.VTVM=1, an attempt to execute SINVAL.VMA in VS-mode also raises a virtual instruction exception.\nHigh-performance implementations will be able to pipeline the address-translation cache invalidation operations, and will defer any pipeline stalls or other memory ordering enforcement until an SFENCE.W.INVAL, SFENCE.INVAL.IR, SFENCE.VMA, HFENCE.GVMA, or HFENCE.VVMA instruction is executed.\nSimpler implementations may implement SINVAL.VMA, HINVAL.VVMA, and HINVAL.GVMA identically to SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively, while implementing SFENCE.W.INVAL and SFENCE.INVAL.IR instructions as no-ops.\n\n\n\n(ISA: supervisor)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-priv-isa-manual/Priv-v1.12/supervisor.html#svinval" }; case "HFENCE.VVMA": return { "html": "

HFENCE.VVMA rs1, rs2

The Svinval extension splits SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA instructions into finer-grained invalidation and ordering operations that can be more efficiently batched or pipelined on certain classes of high-performance implementation.
If the hypervisor extension is implemented, the Svinval extension also provides two additional instructions: HINVAL.VVMA and HINVAL.GVMA. These have the same semantics as SINVAL.VMA, except that they combine with SFENCE.W.INVAL and SFENCE.INVAL.IR to replace HFENCE.VVMA and HFENCE.GVMA, respectively, instead of SFENCE.VMA. In addition, HINVAL.GVMA uses VMIDs instead of ASIDs.
SINVAL.VMA, HINVAL.VVMA, and HINVAL.GVMA require the same permissions and raise the same exceptions as SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively. In particular, an attempt to execute any of these instructions in U-mode always raises an illegal instruction exception, and an attempt to execute SINVAL.VMA or HINVAL.GVMA in S-mode or HS-mode when mstatus.TVM=1 also raises an illegal instruction exception. An attempt to execute HINVAL.VVMA or HINVAL.GVMA in VS-mode or VU-mode, or to execute SINVAL.VMA in VU-mode, raises a virtual instruction exception. When hstatus.VTVM=1, an attempt to execute SINVAL.VMA in VS-mode also raises a virtual instruction exception.
High-performance implementations will be able to pipeline the address-translation cache invalidation operations, and will defer any pipeline stalls or other memory ordering enforcement until an SFENCE.W.INVAL, SFENCE.INVAL.IR, SFENCE.VMA, HFENCE.GVMA, or HFENCE.VVMA instruction is executed.
Simpler implementations may implement SINVAL.VMA, HINVAL.VVMA, and HINVAL.GVMA identically to SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively, while implementing SFENCE.W.INVAL and SFENCE.INVAL.IR instructions as no-ops.

ISA: supervisor

HINVAL.GVMA rs1, rs2

If the hypervisor extension is implemented, the Svinval extension also provides two additional instructions: HINVAL.VVMA and HINVAL.GVMA. These have the same semantics as SINVAL.VMA, except that they combine with SFENCE.W.INVAL and SFENCE.INVAL.IR to replace HFENCE.VVMA and HFENCE.GVMA, respectively, instead of SFENCE.VMA. In addition, HINVAL.GVMA uses VMIDs instead of ASIDs.
SINVAL.VMA, HINVAL.VVMA, and HINVAL.GVMA require the same permissions and raise the same exceptions as SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively. In particular, an attempt to execute any of these instructions in U-mode always raises an illegal instruction exception, and an attempt to execute SINVAL.VMA or HINVAL.GVMA in S-mode or HS-mode when mstatus.TVM=1 also raises an illegal instruction exception. An attempt to execute HINVAL.VVMA or HINVAL.GVMA in VS-mode or VU-mode, or to execute SINVAL.VMA in VU-mode, raises a virtual instruction exception. When hstatus.VTVM=1, an attempt to execute SINVAL.VMA in VS-mode also raises a virtual instruction exception.
In typical usage, software will invalidate a range of virtual addresses in the address-translation caches by executing an SFENCE.W.INVAL instruction, executing a series of SINVAL.VMA, HINVAL.VVMA, or HINVAL.GVMA instructions to the addresses (and optionally ASIDs or VMIDs) in question, and then executing an SFENCE.INVAL.IR instruction.
Simpler implementations may implement SINVAL.VMA, HINVAL.VVMA, and HINVAL.GVMA identically to SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively, while implementing SFENCE.W.INVAL and SFENCE.INVAL.IR instructions as no-ops.

ISA: supervisor

", "tooltip": "If the hypervisor extension is implemented, the Svinval extension also provides two additional instructions: HINVAL.VVMA and HINVAL.GVMA. These have the same semantics as SINVAL.VMA, except that they combine with SFENCE.W.INVAL and SFENCE.INVAL.IR to replace HFENCE.VVMA and HFENCE.GVMA, respectively, instead of SFENCE.VMA. In addition, HINVAL.GVMA uses VMIDs instead of ASIDs.\nSINVAL.VMA, HINVAL.VVMA, and HINVAL.GVMA require the same permissions and raise the same exceptions as SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively. In particular, an attempt to execute any of these instructions in U-mode always raises an illegal instruction exception, and an attempt to execute SINVAL.VMA or HINVAL.GVMA in S-mode or HS-mode when mstatus.TVM=1 also raises an illegal instruction exception. An attempt to execute HINVAL.VVMA or HINVAL.GVMA in VS-mode or VU-mode, or to execute SINVAL.VMA in VU-mode, raises a virtual instruction exception. When hstatus.VTVM=1, an attempt to execute SINVAL.VMA in VS-mode also raises a virtual instruction exception.\nIn typical usage, software will invalidate a range of virtual addresses in the address-translation caches by executing an SFENCE.W.INVAL instruction, executing a series of SINVAL.VMA, HINVAL.VVMA, or HINVAL.GVMA instructions to the addresses (and optionally ASIDs or VMIDs) in question, and then executing an SFENCE.INVAL.IR instruction.\nSimpler implementations may implement SINVAL.VMA, HINVAL.VVMA, and HINVAL.GVMA identically to SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively, while implementing SFENCE.W.INVAL and SFENCE.INVAL.IR instructions as no-ops.\n\n\n\n(ISA: supervisor)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-priv-isa-manual/Priv-v1.12/supervisor.html#svinval" }; case "HINVAL.VVMA": return { "html": "

HINVAL.VVMA rs1, rs2

If the hypervisor extension is implemented, the Svinval extension also provides two additional instructions: HINVAL.VVMA and HINVAL.GVMA. These have the same semantics as SINVAL.VMA, except that they combine with SFENCE.W.INVAL and SFENCE.INVAL.IR to replace HFENCE.VVMA and HFENCE.GVMA, respectively, instead of SFENCE.VMA. In addition, HINVAL.GVMA uses VMIDs instead of ASIDs.
SINVAL.VMA, HINVAL.VVMA, and HINVAL.GVMA require the same permissions and raise the same exceptions as SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively. In particular, an attempt to execute any of these instructions in U-mode always raises an illegal instruction exception, and an attempt to execute SINVAL.VMA or HINVAL.GVMA in S-mode or HS-mode when mstatus.TVM=1 also raises an illegal instruction exception. An attempt to execute HINVAL.VVMA or HINVAL.GVMA in VS-mode or VU-mode, or to execute SINVAL.VMA in VU-mode, raises a virtual instruction exception. When hstatus.VTVM=1, an attempt to execute SINVAL.VMA in VS-mode also raises a virtual instruction exception.
In typical usage, software will invalidate a range of virtual addresses in the address-translation caches by executing an SFENCE.W.INVAL instruction, executing a series of SINVAL.VMA, HINVAL.VVMA, or HINVAL.GVMA instructions to the addresses (and optionally ASIDs or VMIDs) in question, and then executing an SFENCE.INVAL.IR instruction.
Simpler implementations may implement SINVAL.VMA, HINVAL.VVMA, and HINVAL.GVMA identically to SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively, while implementing SFENCE.W.INVAL and SFENCE.INVAL.IR instructions as no-ops.

ISA: supervisor

HLV.B rd, rs1

For every RV32I or RV64I load instruction, LB, LBU, LH, LHU, LW, LWU, and LD, there is a corresponding virtual-machine load instruction: HLV.B, HLV.BU, HLV.H, HLV.HU, HLV.W, HLV.WU, and HLV.D. For every RV32I or RV64I store instruction, SB, SH, SW, and SD, there is a corresponding virtual-machine store instruction: HSV.B, HSV.H, HSV.W, and HSV.D. Instructions HLV.WU, HLV.D, and HSV.D are not valid for RV32, of course.

ISA: hypervisor

HLV.BU rd, rs1

For every RV32I or RV64I load instruction, LB, LBU, LH, LHU, LW, LWU, and LD, there is a corresponding virtual-machine load instruction: HLV.B, HLV.BU, HLV.H, HLV.HU, HLV.W, HLV.WU, and HLV.D. For every RV32I or RV64I store instruction, SB, SH, SW, and SD, there is a corresponding virtual-machine store instruction: HSV.B, HSV.H, HSV.W, and HSV.D. Instructions HLV.WU, HLV.D, and HSV.D are not valid for RV32, of course.

ISA: hypervisor

HLV.D rd, rs1

For every RV32I or RV64I load instruction, LB, LBU, LH, LHU, LW, LWU, and LD, there is a corresponding virtual-machine load instruction: HLV.B, HLV.BU, HLV.H, HLV.HU, HLV.W, HLV.WU, and HLV.D. For every RV32I or RV64I store instruction, SB, SH, SW, and SD, there is a corresponding virtual-machine store instruction: HSV.B, HSV.H, HSV.W, and HSV.D. Instructions HLV.WU, HLV.D, and HSV.D are not valid for RV32, of course.

ISA: hypervisor

HLV.H rd, rs1

For every RV32I or RV64I load instruction, LB, LBU, LH, LHU, LW, LWU, and LD, there is a corresponding virtual-machine load instruction: HLV.B, HLV.BU, HLV.H, HLV.HU, HLV.W, HLV.WU, and HLV.D. For every RV32I or RV64I store instruction, SB, SH, SW, and SD, there is a corresponding virtual-machine store instruction: HSV.B, HSV.H, HSV.W, and HSV.D. Instructions HLV.WU, HLV.D, and HSV.D are not valid for RV32, of course.

ISA: hypervisor

HLV.HU rd, rs1

For every RV32I or RV64I load instruction, LB, LBU, LH, LHU, LW, LWU, and LD, there is a corresponding virtual-machine load instruction: HLV.B, HLV.BU, HLV.H, HLV.HU, HLV.W, HLV.WU, and HLV.D. For every RV32I or RV64I store instruction, SB, SH, SW, and SD, there is a corresponding virtual-machine store instruction: HSV.B, HSV.H, HSV.W, and HSV.D. Instructions HLV.WU, HLV.D, and HSV.D are not valid for RV32, of course.
Instructions HLVX.HU and HLVX.WU are the same as HLV.HU and HLV.WU, except that execute permission takes the place of read permission during address translation. That is, the memory being read must be executable in both stages of address translation, but read permission is not required. For the supervisor physical address that results from address translation, the supervisor physical memory attributes must grant both execute and read permissions. (The supervisor physical memory attributes are the machine's physical memory attributes as modified by physical memory protection, Section [sec:pmp] , for supervisor level.)

ISA: hypervisor

", "tooltip": "For every RV32I or RV64I load instruction, LB, LBU, LH, LHU, LW, LWU, and LD, there is a corresponding virtual-machine load instruction: HLV.B, HLV.BU, HLV.H, HLV.HU, HLV.W, HLV.WU, and HLV.D. For every RV32I or RV64I store instruction, SB, SH, SW, and SD, there is a corresponding virtual-machine store instruction: HSV.B, HSV.H, HSV.W, and HSV.D. Instructions HLV.WU, HLV.D, and HSV.D are not valid for RV32, of course.\nInstructions HLVX.HU and HLVX.WU are the same as HLV.HU and HLV.WU, except that execute permission takes the place of read permission during address translation. That is, the memory being read must be executable in both stages of address translation, but read permission is not required. For the supervisor physical address that results from address translation, the supervisor physical memory attributes must grant both execute and read permissions. (The supervisor physical memory attributes are the machine's physical memory attributes as modified by physical memory protection, Section [sec:pmp] , for supervisor level.)\n\n\n\n(ISA: hypervisor)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-priv-isa-manual/Priv-v1.12/hypervisor.html#hypervisor-virtual-machine-load-and-store-instructions" }; case "HLV.W": return { "html": "

HLV.W rd, rs1

For every RV32I or RV64I load instruction, LB, LBU, LH, LHU, LW, LWU, and LD, there is a corresponding virtual-machine load instruction: HLV.B, HLV.BU, HLV.H, HLV.HU, HLV.W, HLV.WU, and HLV.D. For every RV32I or RV64I store instruction, SB, SH, SW, and SD, there is a corresponding virtual-machine store instruction: HSV.B, HSV.H, HSV.W, and HSV.D. Instructions HLV.WU, HLV.D, and HSV.D are not valid for RV32, of course.
HLVX.WU is valid for RV32, even though LWU and HLV.WU are not. (For RV32, HLVX.WU can be considered a variant of HLV.W, as sign extension is irrelevant for 32-bit values.)

ISA: hypervisor

HLV.WU rd, rs1

For every RV32I or RV64I load instruction, LB, LBU, LH, LHU, LW, LWU, and LD, there is a corresponding virtual-machine load instruction: HLV.B, HLV.BU, HLV.H, HLV.HU, HLV.W, HLV.WU, and HLV.D. For every RV32I or RV64I store instruction, SB, SH, SW, and SD, there is a corresponding virtual-machine store instruction: HSV.B, HSV.H, HSV.W, and HSV.D. Instructions HLV.WU, HLV.D, and HSV.D are not valid for RV32, of course.
Instructions HLVX.HU and HLVX.WU are the same as HLV.HU and HLV.WU, except that execute permission takes the place of read permission during address translation. That is, the memory being read must be executable in both stages of address translation, but read permission is not required. For the supervisor physical address that results from address translation, the supervisor physical memory attributes must grant both execute and read permissions. (The supervisor physical memory attributes are the machine's physical memory attributes as modified by physical memory protection, Section [sec:pmp] , for supervisor level.)
HLVX.WU is valid for RV32, even though LWU and HLV.WU are not. (For RV32, HLVX.WU can be considered a variant of HLV.W, as sign extension is irrelevant for 32-bit values.)

ISA: hypervisor

", "tooltip": "For every RV32I or RV64I load instruction, LB, LBU, LH, LHU, LW, LWU, and LD, there is a corresponding virtual-machine load instruction: HLV.B, HLV.BU, HLV.H, HLV.HU, HLV.W, HLV.WU, and HLV.D. For every RV32I or RV64I store instruction, SB, SH, SW, and SD, there is a corresponding virtual-machine store instruction: HSV.B, HSV.H, HSV.W, and HSV.D. Instructions HLV.WU, HLV.D, and HSV.D are not valid for RV32, of course.\nInstructions HLVX.HU and HLVX.WU are the same as HLV.HU and HLV.WU, except that execute permission takes the place of read permission during address translation. That is, the memory being read must be executable in both stages of address translation, but read permission is not required. For the supervisor physical address that results from address translation, the supervisor physical memory attributes must grant both execute and read permissions. (The supervisor physical memory attributes are the machine's physical memory attributes as modified by physical memory protection, Section [sec:pmp] , for supervisor level.)\nHLVX.WU is valid for RV32, even though LWU and HLV.WU are not. (For RV32, HLVX.WU can be considered a variant of HLV.W, as sign extension is irrelevant for 32-bit values.)\n\n\n\n(ISA: hypervisor)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-priv-isa-manual/Priv-v1.12/hypervisor.html#hypervisor-virtual-machine-load-and-store-instructions" }; case "HLVX.HU": return { "html": "

HLVX.HU rd, rs1

Instructions HLVX.HU and HLVX.WU are the same as HLV.HU and HLV.WU, except that execute permission takes the place of read permission during address translation. That is, the memory being read must be executable in both stages of address translation, but read permission is not required. For the supervisor physical address that results from address translation, the supervisor physical memory attributes must grant both execute and read permissions. (The supervisor physical memory attributes are the machine's physical memory attributes as modified by physical memory protection, Section [sec:pmp] , for supervisor level.)

ISA: hypervisor

", "tooltip": "Instructions HLVX.HU and HLVX.WU are the same as HLV.HU and HLV.WU, except that execute permission takes the place of read permission during address translation. That is, the memory being read must be executable in both stages of address translation, but read permission is not required. For the supervisor physical address that results from address translation, the supervisor physical memory attributes must grant both execute and read permissions. (The supervisor physical memory attributes are the machine's physical memory attributes as modified by physical memory protection, Section [sec:pmp] , for supervisor level.)\n\n\n\n(ISA: hypervisor)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-priv-isa-manual/Priv-v1.12/hypervisor.html#hypervisor-virtual-machine-load-and-store-instructions" }; case "HLVX.WU": return { "html": "

HLVX.WU rd, rs1

Instructions HLVX.HU and HLVX.WU are the same as HLV.HU and HLV.WU, except that execute permission takes the place of read permission during address translation. That is, the memory being read must be executable in both stages of address translation, but read permission is not required. For the supervisor physical address that results from address translation, the supervisor physical memory attributes must grant both execute and read permissions. (The supervisor physical memory attributes are the machine's physical memory attributes as modified by physical memory protection, Section [sec:pmp] , for supervisor level.)
HLVX.WU is valid for RV32, even though LWU and HLV.WU are not. (For RV32, HLVX.WU can be considered a variant of HLV.W, as sign extension is irrelevant for 32-bit values.)

ISA: hypervisor

", "tooltip": "Instructions HLVX.HU and HLVX.WU are the same as HLV.HU and HLV.WU, except that execute permission takes the place of read permission during address translation. That is, the memory being read must be executable in both stages of address translation, but read permission is not required. For the supervisor physical address that results from address translation, the supervisor physical memory attributes must grant both execute and read permissions. (The supervisor physical memory attributes are the machine's physical memory attributes as modified by physical memory protection, Section [sec:pmp] , for supervisor level.)\nHLVX.WU is valid for RV32, even though LWU and HLV.WU are not. (For RV32, HLVX.WU can be considered a variant of HLV.W, as sign extension is irrelevant for 32-bit values.)\n\n\n\n(ISA: hypervisor)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-priv-isa-manual/Priv-v1.12/hypervisor.html#hypervisor-virtual-machine-load-and-store-instructions" }; case "HSV.B": return { "html": "

HSV.B rs1, rs2

For every RV32I or RV64I load instruction, LB, LBU, LH, LHU, LW, LWU, and LD, there is a corresponding virtual-machine load instruction: HLV.B, HLV.BU, HLV.H, HLV.HU, HLV.W, HLV.WU, and HLV.D. For every RV32I or RV64I store instruction, SB, SH, SW, and SD, there is a corresponding virtual-machine store instruction: HSV.B, HSV.H, HSV.W, and HSV.D. Instructions HLV.WU, HLV.D, and HSV.D are not valid for RV32, of course.

ISA: hypervisor

HSV.D rs1, rs2

For every RV32I or RV64I load instruction, LB, LBU, LH, LHU, LW, LWU, and LD, there is a corresponding virtual-machine load instruction: HLV.B, HLV.BU, HLV.H, HLV.HU, HLV.W, HLV.WU, and HLV.D. For every RV32I or RV64I store instruction, SB, SH, SW, and SD, there is a corresponding virtual-machine store instruction: HSV.B, HSV.H, HSV.W, and HSV.D. Instructions HLV.WU, HLV.D, and HSV.D are not valid for RV32, of course.

ISA: hypervisor

HSV.H rs1, rs2

For every RV32I or RV64I load instruction, LB, LBU, LH, LHU, LW, LWU, and LD, there is a corresponding virtual-machine load instruction: HLV.B, HLV.BU, HLV.H, HLV.HU, HLV.W, HLV.WU, and HLV.D. For every RV32I or RV64I store instruction, SB, SH, SW, and SD, there is a corresponding virtual-machine store instruction: HSV.B, HSV.H, HSV.W, and HSV.D. Instructions HLV.WU, HLV.D, and HSV.D are not valid for RV32, of course.

ISA: hypervisor

HSV.W rs1, rs2

For every RV32I or RV64I load instruction, LB, LBU, LH, LHU, LW, LWU, and LD, there is a corresponding virtual-machine load instruction: HLV.B, HLV.BU, HLV.H, HLV.HU, HLV.W, HLV.WU, and HLV.D. For every RV32I or RV64I store instruction, SB, SH, SW, and SD, there is a corresponding virtual-machine store instruction: HSV.B, HSV.H, HSV.W, and HSV.D. Instructions HLV.WU, HLV.D, and HSV.D are not valid for RV32, of course.

ISA: hypervisor

J offset

There are a further two variants of the instruction formats (B/J) based on the handling of immediates, as shown in Figure 1.3 .
Similarly, the only difference between the U and J formats is that the 20-bit immediate is shifted left by 12 bits to form U immediates and by 1 bit to form J immediates. The location of instruction bits in the U and J format immediates is chosen to maximize overlap with the other formats and with each other.
Although more complex implementations might have separate adders for branch and jump calculations and so would not benefit from keeping the location of immediate bits constant across types of instruction, we wanted to reduce the hardware cost of the simplest implementations. By rotating bits in the instruction encoding of B and J immediates instead of using dynamic hardware muxes to multiply the immediate by 2, we reduce instruction signal fanout and immediate mux costs by around a factor of 2. The scrambled immediate encoding will add negligible time to static or ahead-of-time compilation. For dynamic generation of instructions, there is some small additional overhead, but the most common short forward branches have straightforward immediate encodings.

Equivalent ASM:

jal x0, offset

ISA: rv32(pseudo)

", "tooltip": "There are a further two variants of the instruction formats (B/J) based on the handling of immediates, as shown in Figure 1.3 .\nSimilarly, the only difference between the U and J formats is that the 20-bit immediate is shifted left by 12 bits to form U immediates and by 1 bit to form J immediates. The location of instruction bits in the U and J format immediates is chosen to maximize overlap with the other formats and with each other.\nAlthough more complex implementations might have separate adders for branch and jump calculations and so would not benefit from keeping the location of immediate bits constant across types of instruction, we wanted to reduce the hardware cost of the simplest implementations. By rotating bits in the instruction encoding of B and J immediates instead of using dynamic hardware muxes to multiply the immediate by 2, we reduce instruction signal fanout and immediate mux costs by around a factor of 2. The scrambled immediate encoding will add negligible time to static or ahead-of-time compilation. For dynamic generation of instructions, there is some small additional overhead, but the most common short forward branches have straightforward immediate encodings.\n\nEquivalent ASM:\n\njal x0, offset\n\n(ISA: rv32(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#immediate-encoding-variants" }; case "JAL": return { "html": "

JAL rd, jimm20

The current PC can be obtained by setting the U-immediate to 0. Although a JAL +4 instruction could also be used to obtain the local PC (of the instruction following the JAL), it might cause pipeline breaks in simpler microarchitectures or pollute BTB structures in more complex microarchitectures.

ISA: rv32

", "tooltip": "The current PC can be obtained by setting the U-immediate to 0. Although a JAL +4 instruction could also be used to obtain the local PC (of the instruction following the JAL), it might cause pipeline breaks in simpler microarchitectures or pollute BTB structures in more complex microarchitectures.\n\n\n\n(ISA: rv32)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#integer-register-immediate-instructions" }; case "JALR": return { "html": "

JALR rd, rs1, imm12

The AUIPC instruction supports two-instruction sequences to access arbitrary offsets from the PC for both control-flow transfers and data accesses. The combination of an AUIPC and the 12-bit immediate in a JALR can transfer control to any 32-bit PC-relative address, while an AUIPC plus the 12-bit immediate offset in regular load or store instructions can access any 32-bit PC-relative data address.

ISA: rv32

", "tooltip": "The AUIPC instruction supports two-instruction sequences to access arbitrary offsets from the PC for both control-flow transfers and data accesses. The combination of an AUIPC and the 12-bit immediate in a JALR can transfer control to any 32-bit PC-relative address, while an AUIPC plus the 12-bit immediate offset in regular load or store instructions can access any 32-bit PC-relative data address.\n\n\n\n(ISA: rv32)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#integer-register-immediate-instructions" }; case "JR": return { "html": "

JR rs

Equivalent ASM:

jalr x0, rs, 0

ISA: (pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\njalr x0, rs, 0\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "LA": return { "html": "

LA rd, symbol

Equivalent ASM:

auipc rd, symbol@GOT[31:12]\nl{w\\

ISA: (pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\nauipc rd, symbol@GOT[31:12]\nl{w\\\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "LB": return { "html": "

LB rd, rs1, imm12

The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory, then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then zero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values. The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory.

ISA: rv32

", "tooltip": "The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory, then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then zero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values. The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory.\n\n\n\n(ISA: rv32)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#sec:rv32:ldst" }; case "LBU": return { "html": "

LBU rd, rs1, imm12

The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory, then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then zero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values. The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory.

ISA: rv32

LD rd, rs1, imm12

Note that the set of address offsets that can be formed by pairing LUI with LD, AUIPC with JALR, etc.in RV64I is [ - 231 - 211, 231 - 211 - 1].

ISA: rv64

", "tooltip": "Note that the set of address offsets that can be formed by pairing LUI with LD, AUIPC with JALR, etc.in RV64I is [ - 231 - 211, 231 - 211 - 1].\n\n\n\n(ISA: rv64)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv64.html#integer-register-immediate-instructions" }; case "LGA": return { "html": "

LGA rd, symbol

Equivalent ASM:

auipc rd, symbol@GOT[31:12]\nl{w\\

ISA: (pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\nauipc rd, symbol@GOT[31:12]\nl{w\\\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "LH": return { "html": "

LH rd, rs1, imm12

ISA: rv32

LHU rd, rs1, imm12

The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory, then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then zero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values. The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory.

ISA: rv32

LI rd, immediate

Equivalent ASM:

*Myriad sequences*

ISA: (pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\n*Myriad sequences*\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "LLA": return { "html": "

LLA rd, symbol

Equivalent ASM:

auipc rd, symbol[31:12]\naddi rd, rd, symbol[11:0]

ISA: (pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\nauipc rd, symbol[31:12]\naddi rd, rd, symbol[11:0]\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "LR.D": return { "html": "

LR.D rd, rs1

Complex atomic memory operations on a single memory word or doubleword are performed with the load-reserved (LR) and store-conditional (SC) instructions. LR.W loads a word from the address in rs1, places the sign-extended value in rd, and registers a reservation set--a set of bytes that subsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address in rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the bytes being written. If the SC.W succeeds, the instruction writes the word in rs2 to memory, and it writes zero to rd. If the SC.W fails, the instruction does not write to memory, and it writes a nonzero value to rd. Regardless of success or failure, executing an SC.W instruction invalidates any reservation held by this hart. LR.D and SC.D act analogously on doublewords and are only available on RV64. For RV64, LR.W and SC.W sign-extend the value placed in rd.

ISA: a

", "tooltip": "Complex atomic memory operations on a single memory word or doubleword are performed with the load-reserved (LR) and store-conditional (SC) instructions. LR.W loads a word from the address in rs1, places the sign-extended value in rd, and registers a reservation set--a set of bytes that subsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address in rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the bytes being written. If the SC.W succeeds, the instruction writes the word in rs2 to memory, and it writes zero to rd. If the SC.W fails, the instruction does not write to memory, and it writes a nonzero value to rd. Regardless of success or failure, executing an SC.W instruction invalidates any reservation held by this hart. LR.D and SC.D act analogously on doublewords and are only available on RV64. For RV64, LR.W and SC.W sign-extend the value placed in rd.\n\n\n\n(ISA: a)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/a.html#sec:lrsc" }; case "LR.W": return { "html": "

LR.W rd, rs1

Complex atomic memory operations on a single memory word or doubleword are performed with the load-reserved (LR) and store-conditional (SC) instructions. LR.W loads a word from the address in rs1, places the sign-extended value in rd, and registers a reservation set--a set of bytes that subsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address in rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the bytes being written. If the SC.W succeeds, the instruction writes the word in rs2 to memory, and it writes zero to rd. If the SC.W fails, the instruction does not write to memory, and it writes a nonzero value to rd. Regardless of success or failure, executing an SC.W instruction invalidates any reservation held by this hart. LR.D and SC.D act analogously on doublewords and are only available on RV64. For RV64, LR.W and SC.W sign-extend the value placed in rd.

ISA: a

LUI rd, imm20

LUI (load upper immediate) is used to build 32-bit constants and uses the U-type format. LUI places the 32-bit U-immediate value into the destination register rd, filling in the lowest 12 bits with zeros.

ISA: rv32

", "tooltip": "LUI (load upper immediate) is used to build 32-bit constants and uses the U-type format. LUI places the 32-bit U-immediate value into the destination register rd, filling in the lowest 12 bits with zeros.\n\n\n\n(ISA: rv32)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#integer-register-immediate-instructions" }; case "LW": return { "html": "

LW rd, rs1, imm12

ISA: rv32

LWU rd, rs1, imm12

The LW instruction loads a 32-bit value from memory and sign-extends this to 64 bits before storing it in register rd for RV64I. The LWU instruction, on the other hand, zero-extends the 32-bit value from memory for RV64I. LH and LHU are defined analogously for 16-bit values, as are LB and LBU for 8-bit values. The SD, SW, SH, and SB instructions store 64-bit, 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory respectively.

ISA: rv64

", "tooltip": "The LW instruction loads a 32-bit value from memory and sign-extends this to 64 bits before storing it in register rd for RV64I. The LWU instruction, on the other hand, zero-extends the 32-bit value from memory for RV64I. LH and LHU are defined analogously for 16-bit values, as are LB and LBU for 8-bit values. The SD, SW, SH, and SB instructions store 64-bit, 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory respectively.\n\n\n\n(ISA: rv64)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv64.html#load-and-store-instructions" }; case "MAX": return { "html": "

MAX rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "MAXU": return { "html": "

MAXU rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "MIN": return { "html": "

MIN rd, rs1, rs2

MIN

ISA: v

", "tooltip": "MIN\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_register_grouping_vlmul20" }; case "MINU": return { "html": "

MINU rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "MRET": return { "html": "

MRET

An MRET or SRET instruction is used to return from a trap in M-mode or S-mode respectively. When executing an xRET instruction, supposing xPP holds the value y, xIE is set to xPIE; the privilege mode is changed to y; xPIE is set to 1; and xPP is set to the least-privileged supported mode (U if U-mode is implemented, else M). If xPP M, xRET also sets MPRV=0.

ISA: machine

", "tooltip": "An MRET or SRET instruction is used to return from a trap in M-mode or S-mode respectively. When executing an xRET instruction, supposing xPP holds the value y, xIE is set to xPIE; the privilege mode is changed to y; xPIE is set to 1; and xPP is set to the least-privileged supported mode (U if U-mode is implemented, else M). If xPP M, xRET also sets MPRV=0.\n\n\n\n(ISA: machine)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-priv-isa-manual/Priv-v1.12/machine.html#privstack" }; case "MUL": return { "html": "

MUL rd, rs1, rs2

MUL performs an XLEN-bit\u00d7XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but return the upper XLEN bits of the full 2\u00d7XLEN-bit product, for signed\u00d7signed, unsigned\u00d7unsigned, and signedrs1\u00d7unsignedrs2 multiplication, respectively. If both the high and low bits of the same product are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL rdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or rs2). Microarchitectures can then fuse these into a single multiply operation instead of performing two separate multiplies.
In RV64, MUL can be used to obtain the upper 32 bits of the 64-bit product, but signed arguments must be proper 32-bit signed values, whereas unsigned arguments must have their upper 32 bits clear. If the arguments are not known to be sign- or zero-extended, an alternative is to shift both arguments left by 32 bits, then use MULH[[S]U].

ISA: m

", "tooltip": "MUL performs an XLEN-bit\u00d7XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but return the upper XLEN bits of the full 2\u00d7XLEN-bit product, for signed\u00d7signed, unsigned\u00d7unsigned, and signedrs1\u00d7unsignedrs2 multiplication, respectively. If both the high and low bits of the same product are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL rdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or rs2). Microarchitectures can then fuse these into a single multiply operation instead of performing two separate multiplies.\nIn RV64, MUL can be used to obtain the upper 32 bits of the 64-bit product, but signed arguments must be proper 32-bit signed values, whereas unsigned arguments must have their upper 32 bits clear. If the arguments are not known to be sign- or zero-extended, an alternative is to shift both arguments left by 32 bits, then use MULH[[S]U].\n\n\n\n(ISA: m)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/m.html#multiplication-operations" }; case "MULH": return { "html": "

MULH rd, rs1, rs2

MUL performs an XLEN-bit\u00d7XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but return the upper XLEN bits of the full 2\u00d7XLEN-bit product, for signed\u00d7signed, unsigned\u00d7unsigned, and signedrs1\u00d7unsignedrs2 multiplication, respectively. If both the high and low bits of the same product are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL rdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or rs2). Microarchitectures can then fuse these into a single multiply operation instead of performing two separate multiplies.
In RV64, MUL can be used to obtain the upper 32 bits of the 64-bit product, but signed arguments must be proper 32-bit signed values, whereas unsigned arguments must have their upper 32 bits clear. If the arguments are not known to be sign- or zero-extended, an alternative is to shift both arguments left by 32 bits, then use MULH[[S]U].

ISA: m

MULHSU rd, rs1, rs2

MUL performs an XLEN-bit\u00d7XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but return the upper XLEN bits of the full 2\u00d7XLEN-bit product, for signed\u00d7signed, unsigned\u00d7unsigned, and signedrs1\u00d7unsignedrs2 multiplication, respectively. If both the high and low bits of the same product are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL rdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or rs2). Microarchitectures can then fuse these into a single multiply operation instead of performing two separate multiplies.
MULHSU is used in multi-word signed multiplication to multiply the most-significant word of the multiplicand (which contains the sign bit) with the less-significant words of the multiplier (which are unsigned).

ISA: m

", "tooltip": "MUL performs an XLEN-bit\u00d7XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but return the upper XLEN bits of the full 2\u00d7XLEN-bit product, for signed\u00d7signed, unsigned\u00d7unsigned, and signedrs1\u00d7unsignedrs2 multiplication, respectively. If both the high and low bits of the same product are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL rdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or rs2). Microarchitectures can then fuse these into a single multiply operation instead of performing two separate multiplies.\nMULHSU is used in multi-word signed multiplication to multiply the most-significant word of the multiplicand (which contains the sign bit) with the less-significant words of the multiplier (which are unsigned).\n\n\n\n(ISA: m)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/m.html#multiplication-operations" }; case "MULHU": return { "html": "

MULHU rd, rs1, rs2

MUL performs an XLEN-bit\u00d7XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but return the upper XLEN bits of the full 2\u00d7XLEN-bit product, for signed\u00d7signed, unsigned\u00d7unsigned, and signedrs1\u00d7unsignedrs2 multiplication, respectively. If both the high and low bits of the same product are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL rdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or rs2). Microarchitectures can then fuse these into a single multiply operation instead of performing two separate multiplies.

ISA: m

", "tooltip": "MUL performs an XLEN-bit\u00d7XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but return the upper XLEN bits of the full 2\u00d7XLEN-bit product, for signed\u00d7signed, unsigned\u00d7unsigned, and signedrs1\u00d7unsignedrs2 multiplication, respectively. If both the high and low bits of the same product are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL rdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or rs2). Microarchitectures can then fuse these into a single multiply operation instead of performing two separate multiplies.\n\n\n\n(ISA: m)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/m.html#multiplication-operations" }; case "MULW": return { "html": "

MULW rd, rs1, rs2

MULW is an RV64 instruction that multiplies the lower 32 bits of the source registers, placing the sign-extension of the lower 32 bits of the result into the destination register.

ISA: m

", "tooltip": "MULW is an RV64 instruction that multiplies the lower 32 bits of the source registers, placing the sign-extension of the lower 32 bits of the result into the destination register.\n\n\n\n(ISA: m)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/m.html#multiplication-operations" }; case "MV": return { "html": "

MV rd, rs

ADDI adds the sign-extended 12-bit immediate to register rs1. Arithmetic overflow is ignored and the result is simply the low XLEN bits of the result. ADDI rd, rs1, 0 is used to implement the MV rd, rs1 assembler pseudoinstruction.

Equivalent ASM:

addi rd, rs, 0

ISA: rv32(pseudo)

", "tooltip": "ADDI adds the sign-extended 12-bit immediate to register rs1. Arithmetic overflow is ignored and the result is simply the low XLEN bits of the result. ADDI rd, rs1, 0 is used to implement the MV rd, rs1 assembler pseudoinstruction.\n\nEquivalent ASM:\n\naddi rd, rs, 0\n\n(ISA: rv32(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#integer-register-immediate-instructions" }; case "NEG": return { "html": "

NEG rd, rs

The sign-injection instructions provide floating-point MV, ABS, and NEG, as well as supporting a few other operations, including the IEEE copySign operation and sign manipulation in transcendental math function libraries. Although MV, ABS, and NEG only need a single register operand, whereas FSGNJ instructions need two, it is unlikely most microarchitectures would add optimizations to benefit from the reduced number of register reads for these relatively infrequent instructions. Even in this case, a microarchitecture can simply detect when both source registers are the same for FSGNJ instructions and only read a single copy.

Equivalent ASM:

sub rd, x0, rs

ISA: f(pseudo)

", "tooltip": "The sign-injection instructions provide floating-point MV, ABS, and NEG, as well as supporting a few other operations, including the IEEE copySign operation and sign manipulation in transcendental math function libraries. Although MV, ABS, and NEG only need a single register operand, whereas FSGNJ instructions need two, it is unlikely most microarchitectures would add optimizations to benefit from the reduced number of register reads for these relatively infrequent instructions. Even in this case, a microarchitecture can simply detect when both source registers are the same for FSGNJ instructions and only read a single copy.\n\nEquivalent ASM:\n\nsub rd, x0, rs\n\n(ISA: f(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/f.html#single-precision-floating-point-conversion-and-move-instructions" }; case "NEGW": return { "html": "

NEGW rd, rs

Equivalent ASM:

subw rd, x0, rs

ISA: (pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\nsubw rd, x0, rs\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "NOP": return { "html": "

NOP

The NOP instruction does not change any architecturally visible state, except for advancing the pc and incrementing any applicable performance counters. NOP is encoded as ADDI x0, x0, 0.
NOPs can be used to align code segments to microarchitecturally significant address boundaries, or to leave space for inline code modifications. Although there are many possible ways to encode a NOP, we define a canonical NOP encoding to allow microarchitectural optimizations as well as for more readable disassembly output. The other NOP encodings are made available for HINT instructions (Section 1.9 ).
ADDI was chosen for the NOP encoding as this is most likely to take fewest resources to execute across a range of systems (if not optimized away in decode). In particular, the instruction only reads one register. Also, an ADDI functional unit is more likely to be available in a superscalar design as adds are the most common operation. In particular, address-generation functional units can execute ADDI using the same hardware needed for base+offset address calculations, while register-register ADD or logical/shift operations require additional hardware.

Equivalent ASM:

addi x0, x0, 0

ISA: rv32(pseudo)

", "tooltip": "The NOP instruction does not change any architecturally visible state, except for advancing the pc and incrementing any applicable performance counters. NOP is encoded as ADDI x0, x0, 0.\nNOPs can be used to align code segments to microarchitecturally significant address boundaries, or to leave space for inline code modifications. Although there are many possible ways to encode a NOP, we define a canonical NOP encoding to allow microarchitectural optimizations as well as for more readable disassembly output. The other NOP encodings are made available for HINT instructions (Section 1.9 ).\nADDI was chosen for the NOP encoding as this is most likely to take fewest resources to execute across a range of systems (if not optimized away in decode). In particular, the instruction only reads one register. Also, an ADDI functional unit is more likely to be available in a superscalar design as adds are the most common operation. In particular, address-generation functional units can execute ADDI using the same hardware needed for base+offset address calculations, while register-register ADD or logical/shift operations require additional hardware.\n\nEquivalent ASM:\n\naddi x0, x0, 0\n\n(ISA: rv32(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#nop-instruction" }; case "NOT": return { "html": "

NOT rd, rs

ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs a bitwise logical inversion of register rs1 (assembler pseudoinstruction NOT rd, rs).

Equivalent ASM:

xori rd, rs, -1

ISA: rv32(pseudo)

", "tooltip": "ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs a bitwise logical inversion of register rs1 (assembler pseudoinstruction NOT rd, rs).\n\nEquivalent ASM:\n\nxori rd, rs, -1\n\n(ISA: rv32(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#integer-register-immediate-instructions" }; case "OR": return { "html": "

OR rd, rs1, rs2

ADD performs the addition of rs1 and rs2. SUB performs the subtraction of rs2 from rs1. Overflows are ignored and the low XLEN bits of results are written to the destination rd. SLT and SLTU perform signed and unsigned compares respectively, writing 1 to rd if rs1 < rs2, 0 otherwise. Note, SLTU rd, x0, rs2 sets rd to 1 if rs2 is not equal to zero, otherwise sets rd to zero (assembler pseudoinstruction SNEZ rd, rs). AND, OR, and XOR perform bitwise logical operations.

ISA: rv32

ORC.B rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "ORI": return { "html": "

ORI rd, rs1, imm12

ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs a bitwise logical inversion of register rs1 (assembler pseudoinstruction NOT rd, rs).

ISA: rv32

ORN rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "PAUSE": return { "html": "

PAUSE

The PAUSE instruction is a HINT that indicates the current hart's rate of instruction retirement should be temporarily reduced or paused. The duration of its effect must be bounded and may be zero. No architectural state is changed.
Software can use the PAUSE instruction to reduce energy consumption while executing spin-wait code sequences. Multithreaded cores might temporarily relinquish execution resources to other harts when PAUSE is executed. It is recommended that a PAUSE instruction generally be included in the code sequence for a spin-wait loop.
A future extension might add primitives similar to the x86 MONITOR/MWAIT instructions, which provide a more efficient mechanism to wait on writes to a specific memory location. However, these instructions would not supplant PAUSE. PAUSE is more appropriate when polling for non-memory events, when polling for multiple events, or when software does not know precisely what events it is polling for.
The duration of a PAUSE instruction's effect may vary significantly within and among implementations. In typical implementations this duration should be much less than the time to perform a context switch, probably more on the rough order of an on-chip cache miss latency or a cacheless access to main memory.
A series of PAUSE instructions can be used to create a cumulative delay loosely proportional to the number of PAUSE instructions. In spin-wait loops in portable code, however, only one PAUSE instruction should be used before re-evaluating loop conditions, else the hart might stall longer than optimal on some implementations, degrading system performance.
PAUSE is encoded as a FENCE instruction with pred=W, succ=0, fm=0, rd=x0, and rs1=x0.
PAUSE is encoded as a hint within the FENCE opcode because some implementations are expected to deliberately stall the PAUSE instruction until outstanding memory transactions have completed. Because the successor set is null, however, PAUSE does not mandate any particular memory ordering--hence, it truly is a HINT.
Like other FENCE instructions, PAUSE cannot be used within LR/SC sequences without voiding the forward-progress guarantee.
The choice of a predecessor set of W is arbitrary, since the successor set is null. Other HINTs similar to PAUSE might be encoded with other predecessor sets.

ISA: zihintpause

", "tooltip": "The PAUSE instruction is a HINT that indicates the current hart's rate of instruction retirement should be temporarily reduced or paused. The duration of its effect must be bounded and may be zero. No architectural state is changed.\nSoftware can use the PAUSE instruction to reduce energy consumption while executing spin-wait code sequences. Multithreaded cores might temporarily relinquish execution resources to other harts when PAUSE is executed. It is recommended that a PAUSE instruction generally be included in the code sequence for a spin-wait loop.\nA future extension might add primitives similar to the x86 MONITOR/MWAIT instructions, which provide a more efficient mechanism to wait on writes to a specific memory location. However, these instructions would not supplant PAUSE. PAUSE is more appropriate when polling for non-memory events, when polling for multiple events, or when software does not know precisely what events it is polling for.\nThe duration of a PAUSE instruction's effect may vary significantly within and among implementations. In typical implementations this duration should be much less than the time to perform a context switch, probably more on the rough order of an on-chip cache miss latency or a cacheless access to main memory.\nA series of PAUSE instructions can be used to create a cumulative delay loosely proportional to the number of PAUSE instructions. In spin-wait loops in portable code, however, only one PAUSE instruction should be used before re-evaluating loop conditions, else the hart might stall longer than optimal on some implementations, degrading system performance.\nPAUSE is encoded as a FENCE instruction with pred=W, succ=0, fm=0, rd=x0, and rs1=x0.\nPAUSE is encoded as a hint within the FENCE opcode because some implementations are expected to deliberately stall the PAUSE instruction until outstanding memory transactions have completed. Because the successor set is null, however, PAUSE does not mandate any particular memory ordering--hence, it truly is a HINT.\nLike other FENCE instructions, PAUSE cannot be used within LR/SC sequences without voiding the forward-progress guarantee.\nThe choice of a predecessor set of W is arbitrary, since the successor set is null. Other HINTs similar to PAUSE might be encoded with other predecessor sets.\n\n\n\n(ISA: zihintpause)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/zihintpause.html#chap:zihintpause" }; case "PREFETCH.I": return { "html": "

PREFETCH.I rs1, imm12hi

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "PREFETCH.R": return { "html": "

PREFETCH.R rs1, imm12hi

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "PREFETCH.W": return { "html": "

PREFETCH.W rs1, imm12hi

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "RDCYCLE": return { "html": "

RDCYCLE rd

RV32I provides a number of 64-bit read-only user-level counters, which are mapped into the 12-bit CSR address space and accessed in 32-bit pieces using CSRRS instructions. In RV64I, the CSR instructions can manipulate 64-bit CSRs. In particular, the RDCYCLE, RDTIME, and RDINSTRET pseudoinstructions read the full 64 bits of the cycle, time, and instret counters. Hence, the RDCYCLEH, RDTIMEH, and RDINSTRETH instructions are RV32I-only.
The RDCYCLE pseudoinstruction reads the low XLEN bits of the cycle CSR which holds a count of the number of clock cycles executed by the processor core on which the hart is running from an arbitrary start time in the past. RDCYCLEH is an RV32I-only instruction that reads bits 63-32 of the same cycle counter. The underlying 64-bit counter should never overflow in practice. The rate at which the cycle counter advances will depend on the implementation and operating environment. The execution environment should provide a means to determine the current rate (cycles/second) at which the cycle counter is incrementing.
RDCYCLE is intended to return the number of cycles executed by the processor core, not the hart. Precisely defining what is a \"core\" is difficult given some implementation choices (e.g., AMD Bulldozer). Precisely defining what is a \"clock cycle\" is also difficult given the range of implementations (including software emulations), but the intent is that RDCYCLE is used for performance monitoring along with the other performance counters. In particular, where there is one hart/core, one would expect cycle-count/instructions-retired to measure CPI for a hart.
Even though there is no precise definition that works for all platforms, this is still a useful facility for most platforms, and an imprecise, common, \"usually correct\" standard here is better than no standard. The intent of RDCYCLE was primarily performance monitoring/tuning, and the specification was written with that goal in mind.
On some simple platforms, cycle count might represent a valid implementation of RDTIME, in which case RDTIME and RDCYCLE may return the same result.

ISA: counters

", "tooltip": "RV32I provides a number of 64-bit read-only user-level counters, which are mapped into the 12-bit CSR address space and accessed in 32-bit pieces using CSRRS instructions. In RV64I, the CSR instructions can manipulate 64-bit CSRs. In particular, the RDCYCLE, RDTIME, and RDINSTRET pseudoinstructions read the full 64 bits of the cycle, time, and instret counters. Hence, the RDCYCLEH, RDTIMEH, and RDINSTRETH instructions are RV32I-only.\nThe RDCYCLE pseudoinstruction reads the low XLEN bits of the cycle CSR which holds a count of the number of clock cycles executed by the processor core on which the hart is running from an arbitrary start time in the past. RDCYCLEH is an RV32I-only instruction that reads bits 63-32 of the same cycle counter. The underlying 64-bit counter should never overflow in practice. The rate at which the cycle counter advances will depend on the implementation and operating environment. The execution environment should provide a means to determine the current rate (cycles/second) at which the cycle counter is incrementing.\nRDCYCLE is intended to return the number of cycles executed by the processor core, not the hart. Precisely defining what is a \"core\" is difficult given some implementation choices (e.g., AMD Bulldozer). Precisely defining what is a \"clock cycle\" is also difficult given the range of implementations (including software emulations), but the intent is that RDCYCLE is used for performance monitoring along with the other performance counters. In particular, where there is one hart/core, one would expect cycle-count/instructions-retired to measure CPI for a hart.\nEven though there is no precise definition that works for all platforms, this is still a useful facility for most platforms, and an imprecise, common, \"usually correct\" standard here is better than no standard. The intent of RDCYCLE was primarily performance monitoring/tuning, and the specification was written with that goal in mind.\nOn some simple platforms, cycle count might represent a valid implementation of RDTIME, in which case RDTIME and RDCYCLE may return the same result.\n\n\n\n(ISA: counters)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/counters.html#zicntr-standard-extension-for-base-counters-and-timers" }; case "RDCYCLEH": return { "html": "

RDCYCLEH rd

ISA: counters

RDINSTRET rd

ISA: counters

RDINSTRETH rd

ISA: counters

RDTIME rd

ISA: counters

", "tooltip": "RV32I provides a number of 64-bit read-only user-level counters, which are mapped into the 12-bit CSR address space and accessed in 32-bit pieces using CSRRS instructions. In RV64I, the CSR instructions can manipulate 64-bit CSRs. In particular, the RDCYCLE, RDTIME, and RDINSTRET pseudoinstructions read the full 64 bits of the cycle, time, and instret counters. Hence, the RDCYCLEH, RDTIMEH, and RDINSTRETH instructions are RV32I-only.\nThe RDTIME pseudoinstruction reads the low XLEN bits of the time CSR, which counts wall-clock real time that has passed from an arbitrary start time in the past. RDTIMEH is an RV32I-only instruction that reads bits 63-32 of the same real-time counter. The underlying 64-bit counter increments by one with each tick of the real-time clock, and, for realistic real-time clock frequencies, should never overflow in practice. The execution environment should provide a means of determining the period of a counter tick (seconds/tick). The period must be constant. The real-time clocks of all harts in a single user application should be synchronized to within one tick of the real-time clock. The environment should provide a means to determine the accuracy of the clock (i.e., the maximum relative error between the nominal and actual real-time clock periods).\nOn some simple platforms, cycle count might represent a valid implementation of RDTIME, in which case RDTIME and RDCYCLE may return the same result.\n\n\n\n(ISA: counters)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/counters.html#zicntr-standard-extension-for-base-counters-and-timers" }; case "RDTIMEH": return { "html": "

RDTIMEH rd

ISA: counters

REM rd, rs1, rs2

DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by rs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division operation. For REM, the sign of the result equals the sign of the dividend.
If both the quotient and remainder are required from the same division, the recommended code sequence is: DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2 (rdq cannot be the same as rs1 or rs2). Microarchitectures can then fuse these into a single divide operation instead of performing two separate divides.
REM[W]

ISA: m

", "tooltip": "DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by rs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division operation. For REM, the sign of the result equals the sign of the dividend.\nIf both the quotient and remainder are required from the same division, the recommended code sequence is: DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2 (rdq cannot be the same as rs1 or rs2). Microarchitectures can then fuse these into a single divide operation instead of performing two separate divides.\nREM[W]\n\n\n\n(ISA: m)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/m.html#division-operations" }; case "REMU": return { "html": "

REMU rd, rs1, rs2

DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by rs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division operation. For REM, the sign of the result equals the sign of the dividend.
REMU[W]

ISA: m

REMUW rd, rs1, rs2

DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32 bits of rs2, treating them as signed and unsigned integers respectively, placing the 32-bit quotient in rd, sign-extended to 64 bits. REMW and REMUW are RV64 instructions that provide the corresponding signed and unsigned remainder operations respectively. Both REMW and REMUW always sign-extend the 32-bit result to 64 bits, including on a divide by zero.

ISA: m

REMW rd, rs1, rs2

DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32 bits of rs2, treating them as signed and unsigned integers respectively, placing the 32-bit quotient in rd, sign-extended to 64 bits. REMW and REMUW are RV64 instructions that provide the corresponding signed and unsigned remainder operations respectively. Both REMW and REMUW always sign-extend the 32-bit result to 64 bits, including on a divide by zero.

ISA: m

RET

Equivalent ASM:

jalr x0, x1, 0

ISA: (pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\njalr x0, x1, 0\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "REV8": return { "html": "

REV8 rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "ROL": return { "html": "

ROL rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "ROLW": return { "html": "

ROLW rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "ROR": return { "html": "

ROR rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "RORI": return { "html": "

RORI rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "RORIW": return { "html": "

RORIW rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "RORW": return { "html": "

RORW rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SB": return { "html": "

SB rs1, rs2, imm12

ISA: rv32

SBREAK

ECALL and EBREAK were previously named SCALL and SBREAK. The instructions have the same functionality and encoding, but were renamed to reflect that they can be used more generally than to call a supervisor-level operating system or debugger.

ISA: rv32

", "tooltip": "ECALL and EBREAK were previously named SCALL and SBREAK. The instructions have the same functionality and encoding, but were renamed to reflect that they can be used more generally than to call a supervisor-level operating system or debugger.\n\n\n\n(ISA: rv32)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#environment-call-and-breakpoints" }; case "SC.D": return { "html": "

SC.D rd, rs1, rs2

Complex atomic memory operations on a single memory word or doubleword are performed with the load-reserved (LR) and store-conditional (SC) instructions. LR.W loads a word from the address in rs1, places the sign-extended value in rd, and registers a reservation set--a set of bytes that subsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address in rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the bytes being written. If the SC.W succeeds, the instruction writes the word in rs2 to memory, and it writes zero to rd. If the SC.W fails, the instruction does not write to memory, and it writes a nonzero value to rd. Regardless of success or failure, executing an SC.W instruction invalidates any reservation held by this hart. LR.D and SC.D act analogously on doublewords and are only available on RV64. For RV64, LR.W and SC.W sign-extend the value placed in rd.

ISA: a

SC.W rd, rs1, rs2

Complex atomic memory operations on a single memory word or doubleword are performed with the load-reserved (LR) and store-conditional (SC) instructions. LR.W loads a word from the address in rs1, places the sign-extended value in rd, and registers a reservation set--a set of bytes that subsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address in rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the bytes being written. If the SC.W succeeds, the instruction writes the word in rs2 to memory, and it writes zero to rd. If the SC.W fails, the instruction does not write to memory, and it writes a nonzero value to rd. Regardless of success or failure, executing an SC.W instruction invalidates any reservation held by this hart. LR.D and SC.D act analogously on doublewords and are only available on RV64. For RV64, LR.W and SC.W sign-extend the value placed in rd.

ISA: a

SCALL

ECALL and EBREAK were previously named SCALL and SBREAK. The instructions have the same functionality and encoding, but were renamed to reflect that they can be used more generally than to call a supervisor-level operating system or debugger.

ISA: rv32

SD rs1, rs2, imm12

The LW instruction loads a 32-bit value from memory and sign-extends this to 64 bits before storing it in register rd for RV64I. The LWU instruction, on the other hand, zero-extends the 32-bit value from memory for RV64I. LH and LHU are defined analogously for 16-bit values, as are LB and LBU for 8-bit values. The SD, SW, SH, and SB instructions store 64-bit, 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory respectively.

ISA: rv64

SEQZ rd, rs

SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the sign-extended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to XLEN bits then treated as an unsigned number). Note, SLTIU rd, rs1, 1 sets rd to 1 if rs1 equals zero, otherwise sets rd to 0 (assembler pseudoinstruction SEQZ rd, rs).

Equivalent ASM:

sltiu rd, rs, 1

ISA: rv32(pseudo)

", "tooltip": "SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the sign-extended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to XLEN bits then treated as an unsigned number). Note, SLTIU rd, rs1, 1 sets rd to 1 if rs1 equals zero, otherwise sets rd to 0 (assembler pseudoinstruction SEQZ rd, rs).\n\nEquivalent ASM:\n\nsltiu rd, rs, 1\n\n(ISA: rv32(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#integer-register-immediate-instructions" }; case "SEXT.B": return { "html": "

SEXT.B rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SEXT.H": return { "html": "

SEXT.H rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SEXT.W": return { "html": "

SEXT.W rd, rs

ADDIW is an RV64I instruction that adds the sign-extended 12-bit immediate to register rs1 and produces the proper sign-extension of a 32-bit result in rd. Overflows are ignored and the result is the low 32 bits of the result sign-extended to 64 bits. Note, ADDIW rd, rs1, 0 writes the sign-extension of the lower 32 bits of register rs1 into register rd (assembler pseudoinstruction SEXT.W).

Equivalent ASM:

addiw rd, rs, 0

ISA: rv64(pseudo)

", "tooltip": "ADDIW is an RV64I instruction that adds the sign-extended 12-bit immediate to register rs1 and produces the proper sign-extension of a 32-bit result in rd. Overflows are ignored and the result is the low 32 bits of the result sign-extended to 64 bits. Note, ADDIW rd, rs1, 0 writes the sign-extension of the lower 32 bits of register rs1 into register rd (assembler pseudoinstruction SEXT.W).\n\nEquivalent ASM:\n\naddiw rd, rs, 0\n\n(ISA: rv64(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv64.html#integer-register-immediate-instructions" }; case "SFENCE.INVAL.IR": return { "html": "

SFENCE.INVAL.IR

The SINVAL.VMA instruction invalidates any address-translation cache entries that an SFENCE.VMA instruction with the same values of rs1 and rs2 would invalidate. However, unlike SFENCE.VMA, SINVAL.VMA instructions are only ordered with respect to SFENCE.VMA, SFENCE.W.INVAL, and SFENCE.INVAL.IR instructions as defined below.
The SFENCE.W.INVAL instruction guarantees that any previous stores already visible to the current RISC-V hart are ordered before subsequent SINVAL.VMA instructions executed by the same hart. The SFENCE.INVAL.IR instruction guarantees that any previous SINVAL.VMA instructions executed by the current hart are ordered before subsequent implicit references by that hart to the memory-management data structures.
When executed in order (but not necessarily consecutively) by a single hart, the sequence SFENCE.W.INVAL, SINVAL.VMA, and SFENCE.INVAL.IR has the same effect as a hypothetical SFENCE.VMA instruction in which:
reads and writes following the SFENCE.INVAL.IR are considered to be those subsequent to the SFENCE.VMA.
If the hypervisor extension is implemented, the Svinval extension also provides two additional instructions: HINVAL.VVMA and HINVAL.GVMA. These have the same semantics as SINVAL.VMA, except that they combine with SFENCE.W.INVAL and SFENCE.INVAL.IR to replace HFENCE.VVMA and HFENCE.GVMA, respectively, instead of SFENCE.VMA. In addition, HINVAL.GVMA uses VMIDs instead of ASIDs.
SFENCE.W.INVAL and SFENCE.INVAL.IR instructions do not need to be trapped when mstatus.TVM=1 or when hstatus.VTVM=1, as they only have ordering effects but no visible side effects. Trapping of the SINVAL.VMA instruction is sufficient to enable emulation of the intended overall TLB maintenance functionality.
In typical usage, software will invalidate a range of virtual addresses in the address-translation caches by executing an SFENCE.W.INVAL instruction, executing a series of SINVAL.VMA, HINVAL.VVMA, or HINVAL.GVMA instructions to the addresses (and optionally ASIDs or VMIDs) in question, and then executing an SFENCE.INVAL.IR instruction.
High-performance implementations will be able to pipeline the address-translation cache invalidation operations, and will defer any pipeline stalls or other memory ordering enforcement until an SFENCE.W.INVAL, SFENCE.INVAL.IR, SFENCE.VMA, HFENCE.GVMA, or HFENCE.VVMA instruction is executed.
Simpler implementations may implement SINVAL.VMA, HINVAL.VVMA, and HINVAL.GVMA identically to SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively, while implementing SFENCE.W.INVAL and SFENCE.INVAL.IR instructions as no-ops.

ISA: supervisor

", "tooltip": "The SINVAL.VMA instruction invalidates any address-translation cache entries that an SFENCE.VMA instruction with the same values of rs1 and rs2 would invalidate. However, unlike SFENCE.VMA, SINVAL.VMA instructions are only ordered with respect to SFENCE.VMA, SFENCE.W.INVAL, and SFENCE.INVAL.IR instructions as defined below.\nThe SFENCE.W.INVAL instruction guarantees that any previous stores already visible to the current RISC-V hart are ordered before subsequent SINVAL.VMA instructions executed by the same hart. The SFENCE.INVAL.IR instruction guarantees that any previous SINVAL.VMA instructions executed by the current hart are ordered before subsequent implicit references by that hart to the memory-management data structures.\nWhen executed in order (but not necessarily consecutively) by a single hart, the sequence SFENCE.W.INVAL, SINVAL.VMA, and SFENCE.INVAL.IR has the same effect as a hypothetical SFENCE.VMA instruction in which:\nreads and writes following the SFENCE.INVAL.IR are considered to be those subsequent to the SFENCE.VMA.\nIf the hypervisor extension is implemented, the Svinval extension also provides two additional instructions: HINVAL.VVMA and HINVAL.GVMA. These have the same semantics as SINVAL.VMA, except that they combine with SFENCE.W.INVAL and SFENCE.INVAL.IR to replace HFENCE.VVMA and HFENCE.GVMA, respectively, instead of SFENCE.VMA. In addition, HINVAL.GVMA uses VMIDs instead of ASIDs.\nSFENCE.W.INVAL and SFENCE.INVAL.IR instructions do not need to be trapped when mstatus.TVM=1 or when hstatus.VTVM=1, as they only have ordering effects but no visible side effects. Trapping of the SINVAL.VMA instruction is sufficient to enable emulation of the intended overall TLB maintenance functionality.\nIn typical usage, software will invalidate a range of virtual addresses in the address-translation caches by executing an SFENCE.W.INVAL instruction, executing a series of SINVAL.VMA, HINVAL.VVMA, or HINVAL.GVMA instructions to the addresses (and optionally ASIDs or VMIDs) in question, and then executing an SFENCE.INVAL.IR instruction.\nHigh-performance implementations will be able to pipeline the address-translation cache invalidation operations, and will defer any pipeline stalls or other memory ordering enforcement until an SFENCE.W.INVAL, SFENCE.INVAL.IR, SFENCE.VMA, HFENCE.GVMA, or HFENCE.VVMA instruction is executed.\nSimpler implementations may implement SINVAL.VMA, HINVAL.VVMA, and HINVAL.GVMA identically to SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively, while implementing SFENCE.W.INVAL and SFENCE.INVAL.IR instructions as no-ops.\n\n\n\n(ISA: supervisor)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-priv-isa-manual/Priv-v1.12/supervisor.html#svinval" }; case "SFENCE.VMA": return { "html": "

SFENCE.VMA rs1, rs2

This chapter defines the memory model for regular main memory operations. The interaction of the memory model with I/O memory, instruction fetches, FENCE.I, page table walks, and SFENCE.VMA is not (yet) formalized. Some or all of the above may be formalized in a future revision of this specification. The RV128 base ISA and future ISA extensions such as the \"V\" vector and \"J\" JIT extensions will need to be incorporated into a future revision as well.

ISA: rvwmo

", "tooltip": "This chapter defines the memory model for regular main memory operations. The interaction of the memory model with I/O memory, instruction fetches, FENCE.I, page table walks, and SFENCE.VMA is not (yet) formalized. Some or all of the above may be formalized in a future revision of this specification. The RV128 base ISA and future ISA extensions such as the \"V\" vector and \"J\" JIT extensions will need to be incorporated into a future revision as well.\n\n\n\n(ISA: rvwmo)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rvwmo.html#ch:memorymodel" }; case "SFENCE.W.INVAL": return { "html": "

SFENCE.W.INVAL

The SINVAL.VMA instruction invalidates any address-translation cache entries that an SFENCE.VMA instruction with the same values of rs1 and rs2 would invalidate. However, unlike SFENCE.VMA, SINVAL.VMA instructions are only ordered with respect to SFENCE.VMA, SFENCE.W.INVAL, and SFENCE.INVAL.IR instructions as defined below.
The SFENCE.W.INVAL instruction guarantees that any previous stores already visible to the current RISC-V hart are ordered before subsequent SINVAL.VMA instructions executed by the same hart. The SFENCE.INVAL.IR instruction guarantees that any previous SINVAL.VMA instructions executed by the current hart are ordered before subsequent implicit references by that hart to the memory-management data structures.
When executed in order (but not necessarily consecutively) by a single hart, the sequence SFENCE.W.INVAL, SINVAL.VMA, and SFENCE.INVAL.IR has the same effect as a hypothetical SFENCE.VMA instruction in which:
reads and writes prior to the SFENCE.W.INVAL are considered to be those prior to the SFENCE.VMA, and
If the hypervisor extension is implemented, the Svinval extension also provides two additional instructions: HINVAL.VVMA and HINVAL.GVMA. These have the same semantics as SINVAL.VMA, except that they combine with SFENCE.W.INVAL and SFENCE.INVAL.IR to replace HFENCE.VVMA and HFENCE.GVMA, respectively, instead of SFENCE.VMA. In addition, HINVAL.GVMA uses VMIDs instead of ASIDs.
SFENCE.W.INVAL and SFENCE.INVAL.IR instructions do not need to be trapped when mstatus.TVM=1 or when hstatus.VTVM=1, as they only have ordering effects but no visible side effects. Trapping of the SINVAL.VMA instruction is sufficient to enable emulation of the intended overall TLB maintenance functionality.
In typical usage, software will invalidate a range of virtual addresses in the address-translation caches by executing an SFENCE.W.INVAL instruction, executing a series of SINVAL.VMA, HINVAL.VVMA, or HINVAL.GVMA instructions to the addresses (and optionally ASIDs or VMIDs) in question, and then executing an SFENCE.INVAL.IR instruction.
High-performance implementations will be able to pipeline the address-translation cache invalidation operations, and will defer any pipeline stalls or other memory ordering enforcement until an SFENCE.W.INVAL, SFENCE.INVAL.IR, SFENCE.VMA, HFENCE.GVMA, or HFENCE.VVMA instruction is executed.
Simpler implementations may implement SINVAL.VMA, HINVAL.VVMA, and HINVAL.GVMA identically to SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively, while implementing SFENCE.W.INVAL and SFENCE.INVAL.IR instructions as no-ops.

ISA: supervisor

", "tooltip": "The SINVAL.VMA instruction invalidates any address-translation cache entries that an SFENCE.VMA instruction with the same values of rs1 and rs2 would invalidate. However, unlike SFENCE.VMA, SINVAL.VMA instructions are only ordered with respect to SFENCE.VMA, SFENCE.W.INVAL, and SFENCE.INVAL.IR instructions as defined below.\nThe SFENCE.W.INVAL instruction guarantees that any previous stores already visible to the current RISC-V hart are ordered before subsequent SINVAL.VMA instructions executed by the same hart. The SFENCE.INVAL.IR instruction guarantees that any previous SINVAL.VMA instructions executed by the current hart are ordered before subsequent implicit references by that hart to the memory-management data structures.\nWhen executed in order (but not necessarily consecutively) by a single hart, the sequence SFENCE.W.INVAL, SINVAL.VMA, and SFENCE.INVAL.IR has the same effect as a hypothetical SFENCE.VMA instruction in which:\nreads and writes prior to the SFENCE.W.INVAL are considered to be those prior to the SFENCE.VMA, and\nIf the hypervisor extension is implemented, the Svinval extension also provides two additional instructions: HINVAL.VVMA and HINVAL.GVMA. These have the same semantics as SINVAL.VMA, except that they combine with SFENCE.W.INVAL and SFENCE.INVAL.IR to replace HFENCE.VVMA and HFENCE.GVMA, respectively, instead of SFENCE.VMA. In addition, HINVAL.GVMA uses VMIDs instead of ASIDs.\nSFENCE.W.INVAL and SFENCE.INVAL.IR instructions do not need to be trapped when mstatus.TVM=1 or when hstatus.VTVM=1, as they only have ordering effects but no visible side effects. Trapping of the SINVAL.VMA instruction is sufficient to enable emulation of the intended overall TLB maintenance functionality.\nIn typical usage, software will invalidate a range of virtual addresses in the address-translation caches by executing an SFENCE.W.INVAL instruction, executing a series of SINVAL.VMA, HINVAL.VVMA, or HINVAL.GVMA instructions to the addresses (and optionally ASIDs or VMIDs) in question, and then executing an SFENCE.INVAL.IR instruction.\nHigh-performance implementations will be able to pipeline the address-translation cache invalidation operations, and will defer any pipeline stalls or other memory ordering enforcement until an SFENCE.W.INVAL, SFENCE.INVAL.IR, SFENCE.VMA, HFENCE.GVMA, or HFENCE.VVMA instruction is executed.\nSimpler implementations may implement SINVAL.VMA, HINVAL.VVMA, and HINVAL.GVMA identically to SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively, while implementing SFENCE.W.INVAL and SFENCE.INVAL.IR instructions as no-ops.\n\n\n\n(ISA: supervisor)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-priv-isa-manual/Priv-v1.12/supervisor.html#svinval" }; case "SGTZ": return { "html": "

SGTZ rd, rs

Equivalent ASM:

slt rd, x0, rs

ISA: (pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\nslt rd, x0, rs\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SH": return { "html": "

SH rs1, rs2, imm12

ISA: rv32

SH1ADD rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SH1ADD.UW": return { "html": "

SH1ADD.UW rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SH2ADD": return { "html": "

SH2ADD rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SH2ADD.UW": return { "html": "

SH2ADD.UW rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SH3ADD": return { "html": "

SH3ADD rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SH3ADD.UW": return { "html": "

SH3ADD.UW rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SHA256SIG0": return { "html": "

SHA256SIG0 rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SHA256SIG1": return { "html": "

SHA256SIG1 rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SHA256SUM0": return { "html": "

SHA256SUM0 rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SHA256SUM1": return { "html": "

SHA256SUM1 rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SHA512SIG0": return { "html": "

SHA512SIG0 rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SHA512SIG0H": return { "html": "

SHA512SIG0H rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SHA512SIG0L": return { "html": "

SHA512SIG0L rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SHA512SIG1": return { "html": "

SHA512SIG1 rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SHA512SIG1H": return { "html": "

SHA512SIG1H rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SHA512SIG1L": return { "html": "

SHA512SIG1L rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SHA512SUM0": return { "html": "

SHA512SUM0 rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SHA512SUM0R": return { "html": "

SHA512SUM0R rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SHA512SUM1": return { "html": "

SHA512SUM1 rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SHA512SUM1R": return { "html": "

SHA512SUM1R rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SINVAL.VMA": return { "html": "

SINVAL.VMA rs1, rs2

field that supports intercepting supervisor virtual-memory management operations. When TVM=1, attempts to read or write the satp CSR or execute an SFENCE.VMA or SINVAL.VMA instruction while executing in S-mode will raise an illegal instruction exception. When TVM=0, these operations are permitted in S-mode. TVM is read-only 0 when S-mode is not supported.
Trapping satp accesses and the SFENCE.VMA and SINVAL.VMA instructions provides the hooks necessary to lazily populate shadow page tables.

ISA: machine

", "tooltip": "field that supports intercepting supervisor virtual-memory management operations. When TVM=1, attempts to read or write the satp CSR or execute an SFENCE.VMA or SINVAL.VMA instruction while executing in S-mode will raise an illegal instruction exception. When TVM=0, these operations are permitted in S-mode. TVM is read-only 0 when S-mode is not supported.\nTrapping satp accesses and the SFENCE.VMA and SINVAL.VMA instructions provides the hooks necessary to lazily populate shadow page tables.\n\n\n\n(ISA: machine)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-priv-isa-manual/Priv-v1.12/machine.html#virt-control" }; case "SLL": return { "html": "

SLL rd, rs1, rs2

SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2.

ISA: rv32

", "tooltip": "SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2.\n\n\n\n(ISA: rv32)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#integer-register-register-operations" }; case "SLLI": return { "html": "

SLLI rd, rs1

Shifts by a constant are encoded as a specialization of the I-type format. The operand to be shifted is in rs1, and the shift amount is encoded in the lower 5 bits of the I-immediate field. The right shift type is encoded in bit 30. SLLI is a logical left shift (zeros are shifted into the lower bits); SRLI is a logical right shift (zeros are shifted into the upper bits); and SRAI is an arithmetic right shift (the original sign bit is copied into the vacated upper bits).

ISA: rv32

", "tooltip": "Shifts by a constant are encoded as a specialization of the I-type format. The operand to be shifted is in rs1, and the shift amount is encoded in the lower 5 bits of the I-immediate field. The right shift type is encoded in bit 30. SLLI is a logical left shift (zeros are shifted into the lower bits); SRLI is a logical right shift (zeros are shifted into the upper bits); and SRAI is an arithmetic right shift (the original sign bit is copied into the vacated upper bits).\n\n\n\n(ISA: rv32)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#integer-register-immediate-instructions" }; case "SLLI.UW": return { "html": "

SLLI.UW rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SLLI_RV32": return { "html": "

SLLI_RV32 rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SLLIW": return { "html": "

SLLIW rd, rs1

SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. SLLIW, SRLIW, and SRAIW encodings with imm[5] 0 are reserved.
Previously, SLLIW, SRLIW, and SRAIW with imm[5] 0 were defined to cause illegal instruction exceptions, whereas now they are marked as reserved. This is a backwards-compatible change.

ISA: rv64

", "tooltip": "SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. SLLIW, SRLIW, and SRAIW encodings with imm[5] 0 are reserved.\nPreviously, SLLIW, SRLIW, and SRAIW with imm[5] 0 were defined to cause illegal instruction exceptions, whereas now they are marked as reserved. This is a backwards-compatible change.\n\n\n\n(ISA: rv64)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv64.html#integer-register-immediate-instructions" }; case "SLLW": return { "html": "

SLLW rd, rs1, rs2

SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. The shift amount is given by rs2[4:0].

ISA: rv64

", "tooltip": "SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. The shift amount is given by rs2[4:0].\n\n\n\n(ISA: rv64)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv64.html#integer-register-register-operations" }; case "SLT": return { "html": "

SLT rd, rs1, rs2

ADD performs the addition of rs1 and rs2. SUB performs the subtraction of rs2 from rs1. Overflows are ignored and the low XLEN bits of results are written to the destination rd. SLT and SLTU perform signed and unsigned compares respectively, writing 1 to rd if rs1 < rs2, 0 otherwise. Note, SLTU rd, x0, rs2 sets rd to 1 if rs2 is not equal to zero, otherwise sets rd to zero (assembler pseudoinstruction SNEZ rd, rs). AND, OR, and XOR perform bitwise logical operations.

ISA: rv32

SLTI rd, rs1, imm12

SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the sign-extended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to XLEN bits then treated as an unsigned number). Note, SLTIU rd, rs1, 1 sets rd to 1 if rs1 equals zero, otherwise sets rd to 0 (assembler pseudoinstruction SEQZ rd, rs).

ISA: rv32

", "tooltip": "SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the sign-extended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to XLEN bits then treated as an unsigned number). Note, SLTIU rd, rs1, 1 sets rd to 1 if rs1 equals zero, otherwise sets rd to 0 (assembler pseudoinstruction SEQZ rd, rs).\n\n\n\n(ISA: rv32)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#integer-register-immediate-instructions" }; case "SLTIU": return { "html": "

SLTIU rd, rs1, imm12

SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the sign-extended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to XLEN bits then treated as an unsigned number). Note, SLTIU rd, rs1, 1 sets rd to 1 if rs1 equals zero, otherwise sets rd to 0 (assembler pseudoinstruction SEQZ rd, rs).

ISA: rv32

", "tooltip": "SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the sign-extended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to XLEN bits then treated as an unsigned number). Note, SLTIU rd, rs1, 1 sets rd to 1 if rs1 equals zero, otherwise sets rd to 0 (assembler pseudoinstruction SEQZ rd, rs).\n\n\n\n(ISA: rv32)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#integer-register-immediate-instructions" }; case "SLTU": return { "html": "

SLTU rd, rs1, rs2

ADD performs the addition of rs1 and rs2. SUB performs the subtraction of rs2 from rs1. Overflows are ignored and the low XLEN bits of results are written to the destination rd. SLT and SLTU perform signed and unsigned compares respectively, writing 1 to rd if rs1 < rs2, 0 otherwise. Note, SLTU rd, x0, rs2 sets rd to 1 if rs2 is not equal to zero, otherwise sets rd to zero (assembler pseudoinstruction SNEZ rd, rs). AND, OR, and XOR perform bitwise logical operations.

ISA: rv32

SLTZ rd, rs

Equivalent ASM:

slt rd, rs, x0

ISA: (pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\nslt rd, rs, x0\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SM3P0": return { "html": "

SM3P0 rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SM3P1": return { "html": "

SM3P1 rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SM4ED": return { "html": "

SM4ED rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SM4KS": return { "html": "

SM4KS rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SNEZ": return { "html": "

SNEZ rd, rs

ADD performs the addition of rs1 and rs2. SUB performs the subtraction of rs2 from rs1. Overflows are ignored and the low XLEN bits of results are written to the destination rd. SLT and SLTU perform signed and unsigned compares respectively, writing 1 to rd if rs1 < rs2, 0 otherwise. Note, SLTU rd, x0, rs2 sets rd to 1 if rs2 is not equal to zero, otherwise sets rd to zero (assembler pseudoinstruction SNEZ rd, rs). AND, OR, and XOR perform bitwise logical operations.

Equivalent ASM:

sltu rd, x0, rs

ISA: rv32(pseudo)

", "tooltip": "ADD performs the addition of rs1 and rs2. SUB performs the subtraction of rs2 from rs1. Overflows are ignored and the low XLEN bits of results are written to the destination rd. SLT and SLTU perform signed and unsigned compares respectively, writing 1 to rd if rs1 < rs2, 0 otherwise. Note, SLTU rd, x0, rs2 sets rd to 1 if rs2 is not equal to zero, otherwise sets rd to zero (assembler pseudoinstruction SNEZ rd, rs). AND, OR, and XOR perform bitwise logical operations.\n\nEquivalent ASM:\n\nsltu rd, x0, rs\n\n(ISA: rv32(pseudo))", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv32.html#integer-register-register-operations" }; case "SRA": return { "html": "

SRA rd, rs1, rs2

SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2.

ISA: rv32

SRAI rd, rs1

Shifts by a constant are encoded as a specialization of the I-type format. The operand to be shifted is in rs1, and the shift amount is encoded in the lower 5 bits of the I-immediate field. The right shift type is encoded in bit 30. SLLI is a logical left shift (zeros are shifted into the lower bits); SRLI is a logical right shift (zeros are shifted into the upper bits); and SRAI is an arithmetic right shift (the original sign bit is copied into the vacated upper bits).

ISA: rv32

SRAI_RV32 rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SRAIW": return { "html": "

SRAIW rd, rs1

SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. SLLIW, SRLIW, and SRAIW encodings with imm[5] 0 are reserved.
Previously, SLLIW, SRLIW, and SRAIW with imm[5] 0 were defined to cause illegal instruction exceptions, whereas now they are marked as reserved. This is a backwards-compatible change.

ISA: rv64

SRAW rd, rs1, rs2

SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. The shift amount is given by rs2[4:0].

ISA: rv64

SRET

An MRET or SRET instruction is used to return from a trap in M-mode or S-mode respectively. When executing an xRET instruction, supposing xPP holds the value y, xIE is set to xPIE; the privilege mode is changed to y; xPIE is set to 1; and xPP is set to the least-privileged supported mode (U if U-mode is implemented, else M). If xPP M, xRET also sets MPRV=0.

ISA: machine

SRL rd, rs1, rs2

SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2.

ISA: rv32

SRLI rd, rs1

Shifts by a constant are encoded as a specialization of the I-type format. The operand to be shifted is in rs1, and the shift amount is encoded in the lower 5 bits of the I-immediate field. The right shift type is encoded in bit 30. SLLI is a logical left shift (zeros are shifted into the lower bits); SRLI is a logical right shift (zeros are shifted into the upper bits); and SRAI is an arithmetic right shift (the original sign bit is copied into the vacated upper bits).

ISA: rv32

SRLI_RV32 rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "SRLIW": return { "html": "

SRLIW rd, rs1

SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. SLLIW, SRLIW, and SRAIW encodings with imm[5] 0 are reserved.
Previously, SLLIW, SRLIW, and SRAIW with imm[5] 0 were defined to cause illegal instruction exceptions, whereas now they are marked as reserved. This is a backwards-compatible change.

ISA: rv64

SRLW rd, rs1, rs2

SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. The shift amount is given by rs2[4:0].

ISA: rv64

SUB rd, rs1, rs2

ADD performs the addition of rs1 and rs2. SUB performs the subtraction of rs2 from rs1. Overflows are ignored and the low XLEN bits of results are written to the destination rd. SLT and SLTU perform signed and unsigned compares respectively, writing 1 to rd if rs1 < rs2, 0 otherwise. Note, SLTU rd, x0, rs2 sets rd to 1 if rs2 is not equal to zero, otherwise sets rd to zero (assembler pseudoinstruction SNEZ rd, rs). AND, OR, and XOR perform bitwise logical operations.

ISA: rv32

SUBW rd, rs1, rs2

ADDW and SUBW are RV64I-only instructions that are defined analogously to ADD and SUB but operate on 32-bit values and produce signed 32-bit results. Overflows are ignored, and the low 32-bits of the result is sign-extended to 64-bits and written to the destination register.

ISA: rv64

", "tooltip": "ADDW and SUBW are RV64I-only instructions that are defined analogously to ADD and SUB but operate on 32-bit values and produce signed 32-bit results. Overflows are ignored, and the low 32-bits of the result is sign-extended to 64-bits and written to the destination register.\n\n\n\n(ISA: rv64)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-user-isa-manual/Priv-v1.12/rv64.html#integer-register-register-operations" }; case "SW": return { "html": "

SW rs1, rs2, imm12

ISA: rv32

TAIL offset

Equivalent ASM:

auipc x6, offset[31:12]\njalr x0, x6, offset[11:0]

ISA: (pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\nauipc x6, offset[31:12]\njalr x0, x6, offset[11:0]\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "UNZIP": return { "html": "

UNZIP rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAADD.VV": return { "html": "

VAADD.VV vs2, vs1, vd

vaadd

ISA: v

", "tooltip": "vaadd\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VAADD.VX": return { "html": "

VAADD.VX vs2, rs1, vd

vaadd

ISA: v

", "tooltip": "vaadd\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VAADDU.VV": return { "html": "

VAADDU.VV vs2, vs1, vd

The averaging add and subtract instructions right shift the result by one bit and round off the result according to the setting in vxrm. Both unsigned and signed versions are provided. For vaaddu and vaadd there can be no overflow in the result. For vasub and vasubu, overflow is ignored and the result wraps around.
# Averaging add # Averaging adds of unsigned integers. vaaddu.vv vd, vs2, vs1, vm # roundoff_unsigned(vs2[i] + vs1[i], 1) vaaddu.vx vd, vs2, rs1, vm # roundoff_unsigned(vs2[i] + x[rs1], 1) # Averaging adds of signed integers. vaadd.vv vd, vs2, vs1, vm # roundoff_signed(vs2[i] + vs1[i], 1) vaadd.vx vd, vs2, rs1, vm # roundoff_signed(vs2[i] + x[rs1], 1) # Averaging subtract # Averaging subtract of unsigned integers. vasubu.vv vd, vs2, vs1, vm # roundoff_unsigned(vs2[i] - vs1[i], 1) vasubu.vx vd, vs2, rs1, vm # roundoff_unsigned(vs2[i] - x[rs1], 1) # Averaging subtract of signed integers. vasub.vv vd, vs2, vs1, vm # roundoff_signed(vs2[i] - vs1[i], 1) vasub.vx vd, vs2, rs1, vm # roundoff_signed(vs2[i] - x[rs1], 1)

ISA: v

", "tooltip": "The averaging add and subtract instructions right shift the result by one bit and round off the result according to the setting in vxrm. Both unsigned and signed versions are provided. For vaaddu and vaadd there can be no overflow in the result. For vasub and vasubu, overflow is ignored and the result wraps around.\n# Averaging add # Averaging adds of unsigned integers. vaaddu.vv vd, vs2, vs1, vm # roundoff_unsigned(vs2[i] + vs1[i], 1) vaaddu.vx vd, vs2, rs1, vm # roundoff_unsigned(vs2[i] + x[rs1], 1) # Averaging adds of signed integers. vaadd.vv vd, vs2, vs1, vm # roundoff_signed(vs2[i] + vs1[i], 1) vaadd.vx vd, vs2, rs1, vm # roundoff_signed(vs2[i] + x[rs1], 1) # Averaging subtract # Averaging subtract of unsigned integers. vasubu.vv vd, vs2, vs1, vm # roundoff_unsigned(vs2[i] - vs1[i], 1) vasubu.vx vd, vs2, rs1, vm # roundoff_unsigned(vs2[i] - x[rs1], 1) # Averaging subtract of signed integers. vasub.vv vd, vs2, vs1, vm # roundoff_signed(vs2[i] - vs1[i], 1) vasub.vx vd, vs2, rs1, vm # roundoff_signed(vs2[i] - x[rs1], 1)\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_single_width_averaging_add_and_subtract" }; case "VAADDU.VX": return { "html": "

VAADDU.VX vs2, rs1, vd

The averaging add and subtract instructions right shift the result by one bit and round off the result according to the setting in vxrm. Both unsigned and signed versions are provided. For vaaddu and vaadd there can be no overflow in the result. For vasub and vasubu, overflow is ignored and the result wraps around.
# Averaging add # Averaging adds of unsigned integers. vaaddu.vv vd, vs2, vs1, vm # roundoff_unsigned(vs2[i] + vs1[i], 1) vaaddu.vx vd, vs2, rs1, vm # roundoff_unsigned(vs2[i] + x[rs1], 1) # Averaging adds of signed integers. vaadd.vv vd, vs2, vs1, vm # roundoff_signed(vs2[i] + vs1[i], 1) vaadd.vx vd, vs2, rs1, vm # roundoff_signed(vs2[i] + x[rs1], 1) # Averaging subtract # Averaging subtract of unsigned integers. vasubu.vv vd, vs2, vs1, vm # roundoff_unsigned(vs2[i] - vs1[i], 1) vasubu.vx vd, vs2, rs1, vm # roundoff_unsigned(vs2[i] - x[rs1], 1) # Averaging subtract of signed integers. vasub.vv vd, vs2, vs1, vm # roundoff_signed(vs2[i] - vs1[i], 1) vasub.vx vd, vs2, rs1, vm # roundoff_signed(vs2[i] - x[rs1], 1)

ISA: v

VADC.VIM vs2, simm5, vd

vadc and vsbc add or subtract the source operands and the carry-in or borrow-in, and write the result to vector register vd. These instructions are encoded as masked instructions (vm=0), but they operate on and write back all body elements. Encodings corresponding to the unmasked versions (vm=1) are reserved.
For vadc and vsbc, the instruction encoding is reserved if the destination vector register is v0.
# Produce sum with carry. # vd[i] = vs2[i] + vs1[i] + v0.mask[i] vadc.vvm vd, vs2, vs1, v0 # Vector-vector # vd[i] = vs2[i] + x[rs1] + v0.mask[i] vadc.vxm vd, vs2, rs1, v0 # Vector-scalar # vd[i] = vs2[i] + imm + v0.mask[i] vadc.vim vd, vs2, imm, v0 # Vector-immediate # Produce carry out in mask register format # vd.mask[i] = carry_out(vs2[i] + vs1[i] + v0.mask[i]) vmadc.vvm vd, vs2, vs1, v0 # Vector-vector # vd.mask[i] = carry_out(vs2[i] + x[rs1] + v0.mask[i]) vmadc.vxm vd, vs2, rs1, v0 # Vector-scalar # vd.mask[i] = carry_out(vs2[i] + imm + v0.mask[i]) vmadc.vim vd, vs2, imm, v0 # Vector-immediate # vd.mask[i] = carry_out(vs2[i] + vs1[i]) vmadc.vv vd, vs2, vs1 # Vector-vector, no carry-in # vd.mask[i] = carry_out(vs2[i] + x[rs1]) vmadc.vx vd, vs2, rs1 # Vector-scalar, no carry-in # vd.mask[i] = carry_out(vs2[i] + imm) vmadc.vi vd, vs2, imm # Vector-immediate, no carry-in

ISA: v

", "tooltip": "vadc and vsbc add or subtract the source operands and the carry-in or borrow-in, and write the result to vector register vd. These instructions are encoded as masked instructions (vm=0), but they operate on and write back all body elements. Encodings corresponding to the unmasked versions (vm=1) are reserved.\nFor vadc and vsbc, the instruction encoding is reserved if the destination vector register is v0.\n# Produce sum with carry. # vd[i] = vs2[i] + vs1[i] + v0.mask[i] vadc.vvm vd, vs2, vs1, v0 # Vector-vector # vd[i] = vs2[i] + x[rs1] + v0.mask[i] vadc.vxm vd, vs2, rs1, v0 # Vector-scalar # vd[i] = vs2[i] + imm + v0.mask[i] vadc.vim vd, vs2, imm, v0 # Vector-immediate # Produce carry out in mask register format # vd.mask[i] = carry_out(vs2[i] + vs1[i] + v0.mask[i]) vmadc.vvm vd, vs2, vs1, v0 # Vector-vector # vd.mask[i] = carry_out(vs2[i] + x[rs1] + v0.mask[i]) vmadc.vxm vd, vs2, rs1, v0 # Vector-scalar # vd.mask[i] = carry_out(vs2[i] + imm + v0.mask[i]) vmadc.vim vd, vs2, imm, v0 # Vector-immediate # vd.mask[i] = carry_out(vs2[i] + vs1[i]) vmadc.vv vd, vs2, vs1 # Vector-vector, no carry-in # vd.mask[i] = carry_out(vs2[i] + x[rs1]) vmadc.vx vd, vs2, rs1 # Vector-scalar, no carry-in # vd.mask[i] = carry_out(vs2[i] + imm) vmadc.vi vd, vs2, imm # Vector-immediate, no carry-in\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_integer_add_with_carry_subtract_with_borrow_instructions" }; case "VADC.VVM": return { "html": "

VADC.VVM vs2, vs1, vd

vadc and vsbc add or subtract the source operands and the carry-in or borrow-in, and write the result to vector register vd. These instructions are encoded as masked instructions (vm=0), but they operate on and write back all body elements. Encodings corresponding to the unmasked versions (vm=1) are reserved.
For vadc and vsbc, the instruction encoding is reserved if the destination vector register is v0.
# Produce sum with carry. # vd[i] = vs2[i] + vs1[i] + v0.mask[i] vadc.vvm vd, vs2, vs1, v0 # Vector-vector # vd[i] = vs2[i] + x[rs1] + v0.mask[i] vadc.vxm vd, vs2, rs1, v0 # Vector-scalar # vd[i] = vs2[i] + imm + v0.mask[i] vadc.vim vd, vs2, imm, v0 # Vector-immediate # Produce carry out in mask register format # vd.mask[i] = carry_out(vs2[i] + vs1[i] + v0.mask[i]) vmadc.vvm vd, vs2, vs1, v0 # Vector-vector # vd.mask[i] = carry_out(vs2[i] + x[rs1] + v0.mask[i]) vmadc.vxm vd, vs2, rs1, v0 # Vector-scalar # vd.mask[i] = carry_out(vs2[i] + imm + v0.mask[i]) vmadc.vim vd, vs2, imm, v0 # Vector-immediate # vd.mask[i] = carry_out(vs2[i] + vs1[i]) vmadc.vv vd, vs2, vs1 # Vector-vector, no carry-in # vd.mask[i] = carry_out(vs2[i] + x[rs1]) vmadc.vx vd, vs2, rs1 # Vector-scalar, no carry-in # vd.mask[i] = carry_out(vs2[i] + imm) vmadc.vi vd, vs2, imm # Vector-immediate, no carry-in

ISA: v

VADC.VXM vs2, rs1, vd

vadc and vsbc add or subtract the source operands and the carry-in or borrow-in, and write the result to vector register vd. These instructions are encoded as masked instructions (vm=0), but they operate on and write back all body elements. Encodings corresponding to the unmasked versions (vm=1) are reserved.
For vadc and vsbc, the instruction encoding is reserved if the destination vector register is v0.
# Produce sum with carry. # vd[i] = vs2[i] + vs1[i] + v0.mask[i] vadc.vvm vd, vs2, vs1, v0 # Vector-vector # vd[i] = vs2[i] + x[rs1] + v0.mask[i] vadc.vxm vd, vs2, rs1, v0 # Vector-scalar # vd[i] = vs2[i] + imm + v0.mask[i] vadc.vim vd, vs2, imm, v0 # Vector-immediate # Produce carry out in mask register format # vd.mask[i] = carry_out(vs2[i] + vs1[i] + v0.mask[i]) vmadc.vvm vd, vs2, vs1, v0 # Vector-vector # vd.mask[i] = carry_out(vs2[i] + x[rs1] + v0.mask[i]) vmadc.vxm vd, vs2, rs1, v0 # Vector-scalar # vd.mask[i] = carry_out(vs2[i] + imm + v0.mask[i]) vmadc.vim vd, vs2, imm, v0 # Vector-immediate # vd.mask[i] = carry_out(vs2[i] + vs1[i]) vmadc.vv vd, vs2, vs1 # Vector-vector, no carry-in # vd.mask[i] = carry_out(vs2[i] + x[rs1]) vmadc.vx vd, vs2, rs1 # Vector-scalar, no carry-in # vd.mask[i] = carry_out(vs2[i] + imm) vmadc.vi vd, vs2, imm # Vector-immediate, no carry-in

ISA: v

VADD.VI vs2, simm5, vd

# Integer adds. vadd.vv vd, vs2, vs1, vm # Vector-vector vadd.vx vd, vs2, rs1, vm # vector-scalar vadd.vi vd, vs2, imm, vm # vector-immediate # Integer subtract vsub.vv vd, vs2, vs1, vm # Vector-vector vsub.vx vd, vs2, rs1, vm # vector-scalar # Integer reverse subtract vrsub.vx vd, vs2, rs1, vm # vd[i] = x[rs1] - vs2[i] vrsub.vi vd, vs2, imm, vm # vd[i] = imm - vs2[i]

ISA: v

", "tooltip": "# Integer adds. vadd.vv vd, vs2, vs1, vm # Vector-vector vadd.vx vd, vs2, rs1, vm # vector-scalar vadd.vi vd, vs2, imm, vm # vector-immediate # Integer subtract vsub.vv vd, vs2, vs1, vm # Vector-vector vsub.vx vd, vs2, rs1, vm # vector-scalar # Integer reverse subtract vrsub.vx vd, vs2, rs1, vm # vd[i] = x[rs1] - vs2[i] vrsub.vi vd, vs2, imm, vm # vd[i] = imm - vs2[i]\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_single_width_integer_add_and_subtract" }; case "VADD.VV": return { "html": "

VADD.VV vs2, vs1, vd

# Integer adds. vadd.vv vd, vs2, vs1, vm # Vector-vector vadd.vx vd, vs2, rs1, vm # vector-scalar vadd.vi vd, vs2, imm, vm # vector-immediate # Integer subtract vsub.vv vd, vs2, vs1, vm # Vector-vector vsub.vx vd, vs2, rs1, vm # vector-scalar # Integer reverse subtract vrsub.vx vd, vs2, rs1, vm # vd[i] = x[rs1] - vs2[i] vrsub.vi vd, vs2, imm, vm # vd[i] = imm - vs2[i]

ISA: v

VADD.VX vs2, rs1, vd

# Integer adds. vadd.vv vd, vs2, vs1, vm # Vector-vector vadd.vx vd, vs2, rs1, vm # vector-scalar vadd.vi vd, vs2, imm, vm # vector-immediate # Integer subtract vsub.vv vd, vs2, vs1, vm # Vector-vector vsub.vx vd, vs2, rs1, vm # vector-scalar # Integer reverse subtract vrsub.vx vd, vs2, rs1, vm # vd[i] = x[rs1] - vs2[i] vrsub.vi vd, vs2, imm, vm # vd[i] = imm - vs2[i]

ISA: v

VAMOADDEI16.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOADDEI32.V": return { "html": "

VAMOADDEI32.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOADDEI64.V": return { "html": "

VAMOADDEI64.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOADDEI8.V": return { "html": "

VAMOADDEI8.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOANDEI16.V": return { "html": "

VAMOANDEI16.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOANDEI32.V": return { "html": "

VAMOANDEI32.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOANDEI64.V": return { "html": "

VAMOANDEI64.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOANDEI8.V": return { "html": "

VAMOANDEI8.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOMAXEI16.V": return { "html": "

VAMOMAXEI16.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOMAXEI32.V": return { "html": "

VAMOMAXEI32.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOMAXEI64.V": return { "html": "

VAMOMAXEI64.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOMAXEI8.V": return { "html": "

VAMOMAXEI8.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOMAXUEI16.V": return { "html": "

VAMOMAXUEI16.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOMAXUEI32.V": return { "html": "

VAMOMAXUEI32.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOMAXUEI64.V": return { "html": "

VAMOMAXUEI64.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOMAXUEI8.V": return { "html": "

VAMOMAXUEI8.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOMINEI16.V": return { "html": "

VAMOMINEI16.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOMINEI32.V": return { "html": "

VAMOMINEI32.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOMINEI64.V": return { "html": "

VAMOMINEI64.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOMINEI8.V": return { "html": "

VAMOMINEI8.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOMINUEI16.V": return { "html": "

VAMOMINUEI16.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOMINUEI32.V": return { "html": "

VAMOMINUEI32.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOMINUEI64.V": return { "html": "

VAMOMINUEI64.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOMINUEI8.V": return { "html": "

VAMOMINUEI8.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOOREI16.V": return { "html": "

VAMOOREI16.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOOREI32.V": return { "html": "

VAMOOREI32.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOOREI64.V": return { "html": "

VAMOOREI64.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOOREI8.V": return { "html": "

VAMOOREI8.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOSWAPEI16.V": return { "html": "

VAMOSWAPEI16.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOSWAPEI32.V": return { "html": "

VAMOSWAPEI32.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOSWAPEI64.V": return { "html": "

VAMOSWAPEI64.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOSWAPEI8.V": return { "html": "

VAMOSWAPEI8.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOXOREI16.V": return { "html": "

VAMOXOREI16.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOXOREI32.V": return { "html": "

VAMOXOREI32.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOXOREI64.V": return { "html": "

VAMOXOREI64.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAMOXOREI8.V": return { "html": "

VAMOXOREI8.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VAND.VI": return { "html": "

VAND.VI vs2, simm5, vd

# Bitwise logical operations. vand.vv vd, vs2, vs1, vm # Vector-vector vand.vx vd, vs2, rs1, vm # vector-scalar vand.vi vd, vs2, imm, vm # vector-immediate vor.vv vd, vs2, vs1, vm # Vector-vector vor.vx vd, vs2, rs1, vm # vector-scalar vor.vi vd, vs2, imm, vm # vector-immediate vxor.vv vd, vs2, vs1, vm # Vector-vector vxor.vx vd, vs2, rs1, vm # vector-scalar vxor.vi vd, vs2, imm, vm # vector-immediate

ISA: v

", "tooltip": "# Bitwise logical operations. vand.vv vd, vs2, vs1, vm # Vector-vector vand.vx vd, vs2, rs1, vm # vector-scalar vand.vi vd, vs2, imm, vm # vector-immediate vor.vv vd, vs2, vs1, vm # Vector-vector vor.vx vd, vs2, rs1, vm # vector-scalar vor.vi vd, vs2, imm, vm # vector-immediate vxor.vv vd, vs2, vs1, vm # Vector-vector vxor.vx vd, vs2, rs1, vm # vector-scalar vxor.vi vd, vs2, imm, vm # vector-immediate\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_bitwise_logical_instructions" }; case "VAND.VV": return { "html": "

VAND.VV vs2, vs1, vd

# Bitwise logical operations. vand.vv vd, vs2, vs1, vm # Vector-vector vand.vx vd, vs2, rs1, vm # vector-scalar vand.vi vd, vs2, imm, vm # vector-immediate vor.vv vd, vs2, vs1, vm # Vector-vector vor.vx vd, vs2, rs1, vm # vector-scalar vor.vi vd, vs2, imm, vm # vector-immediate vxor.vv vd, vs2, vs1, vm # Vector-vector vxor.vx vd, vs2, rs1, vm # vector-scalar vxor.vi vd, vs2, imm, vm # vector-immediate

ISA: v

VAND.VX vs2, rs1, vd

# Bitwise logical operations. vand.vv vd, vs2, vs1, vm # Vector-vector vand.vx vd, vs2, rs1, vm # vector-scalar vand.vi vd, vs2, imm, vm # vector-immediate vor.vv vd, vs2, vs1, vm # Vector-vector vor.vx vd, vs2, rs1, vm # vector-scalar vor.vi vd, vs2, imm, vm # vector-immediate vxor.vv vd, vs2, vs1, vm # Vector-vector vxor.vx vd, vs2, rs1, vm # vector-scalar vxor.vi vd, vs2, imm, vm # vector-immediate

ISA: v

VASUB.VV vs2, vs1, vd

vasub

ISA: v

", "tooltip": "vasub\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VASUB.VX": return { "html": "

VASUB.VX vs2, rs1, vd

vasub

ISA: v

", "tooltip": "vasub\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VASUBU.VV": return { "html": "

VASUBU.VV vs2, vs1, vd

vasubu

ISA: v

", "tooltip": "vasubu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VASUBU.VX": return { "html": "

VASUBU.VX vs2, rs1, vd

vasubu

ISA: v

", "tooltip": "vasubu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VCOMPRESS.VM": return { "html": "

VCOMPRESS.VM vs2, vs1, vd

vcompress is encoded as an unmasked instruction (vm=1). The equivalent masked instruction (vm=0) is reserved.
A trap on a vcompress instruction is always reported with a vstart of 0. Executing a vcompress instruction with a non-zero vstart raises an illegal instruction exception.
vcompress.vm vd, vs2, vs1 # Compress into vd elements of vs2 where vs1 is enabled
Example use of vcompress instruction 8 7 6 5 4 3 2 1 0 Element number 1 1 0 1 0 0 1 0 1 v0 8 7 6 5 4 3 2 1 0 v1 1 2 3 4 5 6 7 8 9 v2 vcompress.vm v2, v1, v0 1 2 3 4 8 7 5 2 0 v2

ISA: v

", "tooltip": "vcompress is encoded as an unmasked instruction (vm=1). The equivalent masked instruction (vm=0) is reserved.\nA trap on a vcompress instruction is always reported with a vstart of 0. Executing a vcompress instruction with a non-zero vstart raises an illegal instruction exception.\nvcompress.vm vd, vs2, vs1 # Compress into vd elements of vs2 where vs1 is enabled\nExample use of vcompress instruction 8 7 6 5 4 3 2 1 0 Element number 1 1 0 1 0 0 1 0 1 v0 8 7 6 5 4 3 2 1 0 v1 1 2 3 4 5 6 7 8 9 v2 vcompress.vm v2, v1, v0 1 2 3 4 8 7 5 2 0 v2\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_compress_instruction" }; case "VCPOP.M": return { "html": "

VCPOP.M vs2, rd

The vcpop.m instruction counts the number of mask elements of the active elements of the vector source mask register that have the value 1 and writes the result to a scalar x register.
The vcpop.m instruction writes x[rd] even if vl=0 (with the value 0, since no mask elements are active).
Traps on vcpop.m are always reported with a vstart of 0. The vcpop.m instruction will raise an illegal instruction exception if vstart is non-zero.
vcpop.m rd, vs2, vm
vcpop.m rd, vs2, v0.t # x[rd] = sum_i ( vs2.mask[i] && v0.mask[i] )

ISA: v

", "tooltip": "The vcpop.m instruction counts the number of mask elements of the active elements of the vector source mask register that have the value 1 and writes the result to a scalar x register.\nThe vcpop.m instruction writes x[rd] even if vl=0 (with the value 0, since no mask elements are active).\nTraps on vcpop.m are always reported with a vstart of 0. The vcpop.m instruction will raise an illegal instruction exception if vstart is non-zero.\nvcpop.m rd, vs2, vm\nvcpop.m rd, vs2, v0.t # x[rd] = sum_i ( vs2.mask[i] && v0.mask[i] )\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_count_population_in_mask_vcpop_m" }; case "VDIV.VV": return { "html": "

VDIV.VV vs2, vs1, vd

vdiv

ISA: v

", "tooltip": "vdiv\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VDIV.VX": return { "html": "

VDIV.VX vs2, rs1, vd

vdiv

ISA: v

", "tooltip": "vdiv\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VDIVU.VV": return { "html": "

VDIVU.VV vs2, vs1, vd

# Unsigned divide. vdivu.vv vd, vs2, vs1, vm # Vector-vector vdivu.vx vd, vs2, rs1, vm # vector-scalar # Signed divide vdiv.vv vd, vs2, vs1, vm # Vector-vector vdiv.vx vd, vs2, rs1, vm # vector-scalar # Unsigned remainder vremu.vv vd, vs2, vs1, vm # Vector-vector vremu.vx vd, vs2, rs1, vm # vector-scalar # Signed remainder vrem.vv vd, vs2, vs1, vm # Vector-vector vrem.vx vd, vs2, rs1, vm # vector-scalar

ISA: v

", "tooltip": "# Unsigned divide. vdivu.vv vd, vs2, vs1, vm # Vector-vector vdivu.vx vd, vs2, rs1, vm # vector-scalar # Signed divide vdiv.vv vd, vs2, vs1, vm # Vector-vector vdiv.vx vd, vs2, rs1, vm # vector-scalar # Unsigned remainder vremu.vv vd, vs2, vs1, vm # Vector-vector vremu.vx vd, vs2, rs1, vm # vector-scalar # Signed remainder vrem.vv vd, vs2, vs1, vm # Vector-vector vrem.vx vd, vs2, rs1, vm # vector-scalar\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_integer_divide_instructions" }; case "VDIVU.VX": return { "html": "

VDIVU.VX vs2, rs1, vd

# Unsigned divide. vdivu.vv vd, vs2, vs1, vm # Vector-vector vdivu.vx vd, vs2, rs1, vm # vector-scalar # Signed divide vdiv.vv vd, vs2, vs1, vm # Vector-vector vdiv.vx vd, vs2, rs1, vm # vector-scalar # Unsigned remainder vremu.vv vd, vs2, vs1, vm # Vector-vector vremu.vx vd, vs2, rs1, vm # vector-scalar # Signed remainder vrem.vv vd, vs2, vs1, vm # Vector-vector vrem.vx vd, vs2, rs1, vm # vector-scalar

ISA: v

VFADD.VF vs2, rs1, vd

# Floating-point add vfadd.vv vd, vs2, vs1, vm # Vector-vector vfadd.vf vd, vs2, rs1, vm # vector-scalar # Floating-point subtract vfsub.vv vd, vs2, vs1, vm # Vector-vector vfsub.vf vd, vs2, rs1, vm # Vector-scalar vd[i] = vs2[i] - f[rs1] vfrsub.vf vd, vs2, rs1, vm # Scalar-vector vd[i] = f[rs1] - vs2[i]

ISA: v

", "tooltip": "# Floating-point add vfadd.vv vd, vs2, vs1, vm # Vector-vector vfadd.vf vd, vs2, rs1, vm # vector-scalar # Floating-point subtract vfsub.vv vd, vs2, vs1, vm # Vector-vector vfsub.vf vd, vs2, rs1, vm # Vector-scalar vd[i] = vs2[i] - f[rs1] vfrsub.vf vd, vs2, rs1, vm # Scalar-vector vd[i] = f[rs1] - vs2[i]\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_single_width_floating_point_addsubtract_instructions" }; case "VFADD.VV": return { "html": "

VFADD.VV vs2, vs1, vd

# Floating-point add vfadd.vv vd, vs2, vs1, vm # Vector-vector vfadd.vf vd, vs2, rs1, vm # vector-scalar # Floating-point subtract vfsub.vv vd, vs2, vs1, vm # Vector-vector vfsub.vf vd, vs2, rs1, vm # Vector-scalar vd[i] = vs2[i] - f[rs1] vfrsub.vf vd, vs2, rs1, vm # Scalar-vector vd[i] = f[rs1] - vs2[i]

ISA: v

VFCLASS.V vs2, vd

vfclass.v vd, vs2, vm # Vector-vector

ISA: v

", "tooltip": "vfclass.v vd, vs2, vm # Vector-vector\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_floating_point_classify_instruction" }; case "VFCVT.F.X.V": return { "html": "

VFCVT.F.X.V vs2, vd

vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. vfcvt.rtz.xu.f.v vd, vs2, vm # Convert float to unsigned integer, truncating. vfcvt.rtz.x.f.v vd, vs2, vm # Convert float to signed integer, truncating. vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. vfcvt.f.x.v vd, vs2, vm # Convert signed integer to float.

ISA: v

", "tooltip": "vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. vfcvt.rtz.xu.f.v vd, vs2, vm # Convert float to unsigned integer, truncating. vfcvt.rtz.x.f.v vd, vs2, vm # Convert float to signed integer, truncating. vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. vfcvt.f.x.v vd, vs2, vm # Convert signed integer to float.\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_single_width_floating_pointinteger_type_convert_instructions" }; case "VFCVT.F.XU.V": return { "html": "

VFCVT.F.XU.V vs2, vd

vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. vfcvt.rtz.xu.f.v vd, vs2, vm # Convert float to unsigned integer, truncating. vfcvt.rtz.x.f.v vd, vs2, vm # Convert float to signed integer, truncating. vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. vfcvt.f.x.v vd, vs2, vm # Convert signed integer to float.

ISA: v

VFCVT.RTZ.X.F.V vs2, vd

vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. vfcvt.rtz.xu.f.v vd, vs2, vm # Convert float to unsigned integer, truncating. vfcvt.rtz.x.f.v vd, vs2, vm # Convert float to signed integer, truncating. vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. vfcvt.f.x.v vd, vs2, vm # Convert signed integer to float.

ISA: v

VFCVT.RTZ.XU.F.V vs2, vd

vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. vfcvt.rtz.xu.f.v vd, vs2, vm # Convert float to unsigned integer, truncating. vfcvt.rtz.x.f.v vd, vs2, vm # Convert float to signed integer, truncating. vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. vfcvt.f.x.v vd, vs2, vm # Convert signed integer to float.

ISA: v

VFCVT.X.F.V vs2, vd

vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. vfcvt.rtz.xu.f.v vd, vs2, vm # Convert float to unsigned integer, truncating. vfcvt.rtz.x.f.v vd, vs2, vm # Convert float to signed integer, truncating. vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. vfcvt.f.x.v vd, vs2, vm # Convert signed integer to float.

ISA: v

VFCVT.XU.F.V vs2, vd

vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. vfcvt.rtz.xu.f.v vd, vs2, vm # Convert float to unsigned integer, truncating. vfcvt.rtz.x.f.v vd, vs2, vm # Convert float to signed integer, truncating. vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. vfcvt.f.x.v vd, vs2, vm # Convert signed integer to float.

ISA: v

VFDIV.VF vs2, rs1, vd

vfdiv

ISA: v

", "tooltip": "vfdiv\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFDIV.VV": return { "html": "

VFDIV.VV vs2, vs1, vd

vfdiv

ISA: v

", "tooltip": "vfdiv\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFIRST.M": return { "html": "

VFIRST.M vs2, rd

The vfirst instruction finds the lowest-numbered active element of the source mask vector that has the value 1 and writes that element's index to a GPR. If no active element has the value 1, -1 is written to the GPR.
The vfirst.m instruction writes x[rd] even if vl=0 (with the value -1, since no mask elements are active).
Traps on vfirst are always reported with a vstart of 0. The vfirst instruction will raise an illegal instruction exception if vstart is non-zero.
vfirst.m rd, vs2, vm

ISA: v

", "tooltip": "The vfirst instruction finds the lowest-numbered active element of the source mask vector that has the value 1 and writes that element's index to a GPR. If no active element has the value 1, -1 is written to the GPR.\nThe vfirst.m instruction writes x[rd] even if vl=0 (with the value -1, since no mask elements are active).\nTraps on vfirst are always reported with a vstart of 0. The vfirst instruction will raise an illegal instruction exception if vstart is non-zero.\nvfirst.m rd, vs2, vm\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vfirst_find_first_set_mask_bit" }; case "VFMACC.VF": return { "html": "

VFMACC.VF vs2, rs1, vd

# FP multiply-accumulate, overwrites addend vfmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vfmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i] # FP negate-(multiply-accumulate), overwrites subtrahend vfnmacc.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) - vd[i] vfnmacc.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) - vd[i] # FP multiply-subtract-accumulator, overwrites subtrahend vfmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) - vd[i] vfmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) - vd[i] # FP negate-(multiply-subtract-accumulator), overwrites minuend vfnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] vfnmsac.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) + vd[i] # FP multiply-add, overwrites multiplicand vfmadd.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vd[i]) + vs2[i] vfmadd.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vd[i]) + vs2[i] # FP negate-(multiply-add), overwrites multiplicand vfnmadd.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) - vs2[i] vfnmadd.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vd[i]) - vs2[i] # FP multiply-sub, overwrites multiplicand vfmsub.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vd[i]) - vs2[i] vfmsub.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vd[i]) - vs2[i] # FP negate-(multiply-sub), overwrites multiplicand vfnmsub.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) + vs2[i] vfnmsub.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vd[i]) + vs2[i]

ISA: v

", "tooltip": "# FP multiply-accumulate, overwrites addend vfmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vfmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i] # FP negate-(multiply-accumulate), overwrites subtrahend vfnmacc.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) - vd[i] vfnmacc.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) - vd[i] # FP multiply-subtract-accumulator, overwrites subtrahend vfmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) - vd[i] vfmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) - vd[i] # FP negate-(multiply-subtract-accumulator), overwrites minuend vfnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] vfnmsac.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) + vd[i] # FP multiply-add, overwrites multiplicand vfmadd.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vd[i]) + vs2[i] vfmadd.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vd[i]) + vs2[i] # FP negate-(multiply-add), overwrites multiplicand vfnmadd.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) - vs2[i] vfnmadd.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vd[i]) - vs2[i] # FP multiply-sub, overwrites multiplicand vfmsub.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vd[i]) - vs2[i] vfmsub.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vd[i]) - vs2[i] # FP negate-(multiply-sub), overwrites multiplicand vfnmsub.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) + vs2[i] vfnmsub.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vd[i]) + vs2[i]\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_single_width_floating_point_fused_multiply_add_instructions" }; case "VFMACC.VV": return { "html": "

VFMACC.VV vs2, vs1, vd

# FP multiply-accumulate, overwrites addend vfmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vfmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i] # FP negate-(multiply-accumulate), overwrites subtrahend vfnmacc.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) - vd[i] vfnmacc.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) - vd[i] # FP multiply-subtract-accumulator, overwrites subtrahend vfmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) - vd[i] vfmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) - vd[i] # FP negate-(multiply-subtract-accumulator), overwrites minuend vfnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] vfnmsac.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) + vd[i] # FP multiply-add, overwrites multiplicand vfmadd.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vd[i]) + vs2[i] vfmadd.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vd[i]) + vs2[i] # FP negate-(multiply-add), overwrites multiplicand vfnmadd.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) - vs2[i] vfnmadd.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vd[i]) - vs2[i] # FP multiply-sub, overwrites multiplicand vfmsub.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vd[i]) - vs2[i] vfmsub.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vd[i]) - vs2[i] # FP negate-(multiply-sub), overwrites multiplicand vfnmsub.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) + vs2[i] vfnmsub.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vd[i]) + vs2[i]

ISA: v

VFMADD.VF vs2, rs1, vd

vfmadd

ISA: v

", "tooltip": "vfmadd\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFMADD.VV": return { "html": "

VFMADD.VV vs2, vs1, vd

vfmadd

ISA: v

", "tooltip": "vfmadd\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFMAX.VF": return { "html": "

VFMAX.VF vs2, rs1, vd

vfmax

ISA: v

", "tooltip": "vfmax\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFMAX.VV": return { "html": "

VFMAX.VV vs2, vs1, vd

vfmax

ISA: v

", "tooltip": "vfmax\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFMERGE.VFM": return { "html": "

VFMERGE.VFM vs2, rs1, vd

The vfmerge.vfm instruction is encoded as a masked instruction (vm=0). At elements where the mask value is zero, the first vector operand is copied to the destination element, otherwise a scalar floating-point register value is copied to the destination element.
vfmerge.vfm vd, vs2, rs1, v0 # vd[i] = v0.mask[i] ? f[rs1] : vs2[i]

ISA: v

", "tooltip": "The vfmerge.vfm instruction is encoded as a masked instruction (vm=0). At elements where the mask value is zero, the first vector operand is copied to the destination element, otherwise a scalar floating-point register value is copied to the destination element.\nvfmerge.vfm vd, vs2, rs1, v0 # vd[i] = v0.mask[i] ? f[rs1] : vs2[i]\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_floating_point_merge_instruction" }; case "VFMIN.VF": return { "html": "

VFMIN.VF vs2, rs1, vd

The vector floating-point vfmin and vfmax instructions have the same behavior as the corresponding scalar floating-point instructions in version 2.2 of the RISC-V F/D/Q extension.
# Floating-point minimum vfmin.vv vd, vs2, vs1, vm # Vector-vector vfmin.vf vd, vs2, rs1, vm # vector-scalar # Floating-point maximum vfmax.vv vd, vs2, vs1, vm # Vector-vector vfmax.vf vd, vs2, rs1, vm # vector-scalar

ISA: v

", "tooltip": "The vector floating-point vfmin and vfmax instructions have the same behavior as the corresponding scalar floating-point instructions in version 2.2 of the RISC-V F/D/Q extension.\n# Floating-point minimum vfmin.vv vd, vs2, vs1, vm # Vector-vector vfmin.vf vd, vs2, rs1, vm # vector-scalar # Floating-point maximum vfmax.vv vd, vs2, vs1, vm # Vector-vector vfmax.vf vd, vs2, rs1, vm # vector-scalar\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_floating_point_minmax_instructions" }; case "VFMIN.VV": return { "html": "

VFMIN.VV vs2, vs1, vd

The vector floating-point vfmin and vfmax instructions have the same behavior as the corresponding scalar floating-point instructions in version 2.2 of the RISC-V F/D/Q extension.
# Floating-point minimum vfmin.vv vd, vs2, vs1, vm # Vector-vector vfmin.vf vd, vs2, rs1, vm # vector-scalar # Floating-point maximum vfmax.vv vd, vs2, vs1, vm # Vector-vector vfmax.vf vd, vs2, rs1, vm # vector-scalar

ISA: v

VFMSAC.VF vs2, rs1, vd

vfmsac

ISA: v

", "tooltip": "vfmsac\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFMSAC.VV": return { "html": "

VFMSAC.VV vs2, vs1, vd

vfmsac

ISA: v

", "tooltip": "vfmsac\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFMSUB.VF": return { "html": "

VFMSUB.VF vs2, rs1, vd

vfmsub

ISA: v

", "tooltip": "vfmsub\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFMSUB.VV": return { "html": "

VFMSUB.VV vs2, vs1, vd

vfmsub

ISA: v

", "tooltip": "vfmsub\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFMUL.VF": return { "html": "

VFMUL.VF vs2, rs1, vd

# Floating-point multiply vfmul.vv vd, vs2, vs1, vm # Vector-vector vfmul.vf vd, vs2, rs1, vm # vector-scalar # Floating-point divide vfdiv.vv vd, vs2, vs1, vm # Vector-vector vfdiv.vf vd, vs2, rs1, vm # vector-scalar # Reverse floating-point divide vector = scalar / vector vfrdiv.vf vd, vs2, rs1, vm # scalar-vector, vd[i] = f[rs1]/vs2[i]

ISA: v

", "tooltip": "# Floating-point multiply vfmul.vv vd, vs2, vs1, vm # Vector-vector vfmul.vf vd, vs2, rs1, vm # vector-scalar # Floating-point divide vfdiv.vv vd, vs2, vs1, vm # Vector-vector vfdiv.vf vd, vs2, rs1, vm # vector-scalar # Reverse floating-point divide vector = scalar / vector vfrdiv.vf vd, vs2, rs1, vm # scalar-vector, vd[i] = f[rs1]/vs2[i]\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_single_width_floating_point_multiplydivide_instructions" }; case "VFMUL.VV": return { "html": "

VFMUL.VV vs2, vs1, vd

# Floating-point multiply vfmul.vv vd, vs2, vs1, vm # Vector-vector vfmul.vf vd, vs2, rs1, vm # vector-scalar # Floating-point divide vfdiv.vv vd, vs2, vs1, vm # Vector-vector vfdiv.vf vd, vs2, rs1, vm # vector-scalar # Reverse floating-point divide vector = scalar / vector vfrdiv.vf vd, vs2, rs1, vm # scalar-vector, vd[i] = f[rs1]/vs2[i]

ISA: v

VFMV.F.S vs2, rd

vfmv.v.f vd, rs1 # vd[i] = f[rs1]

ISA: v

", "tooltip": "vfmv.v.f vd, rs1 # vd[i] = f[rs1]\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_floating_point_move_instruction" }; case "VFMV.S.F": return { "html": "

VFMV.S.F rs1, vd

vfmv.v.f vd, rs1 # vd[i] = f[rs1]

ISA: v

VFMV.V.F rs1, vd

vfmv.v.f vd, rs1 # vd[i] = f[rs1]

ISA: v

VFNCVT.F.F.W vs2, vd

vfncvt.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer. vfncvt.x.f.w vd, vs2, vm # Convert double-width float to signed integer. vfncvt.rtz.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer, truncating. vfncvt.rtz.x.f.w vd, vs2, vm # Convert double-width float to signed integer, truncating. vfncvt.f.xu.w vd, vs2, vm # Convert double-width unsigned integer to float. vfncvt.f.x.w vd, vs2, vm # Convert double-width signed integer to float. vfncvt.f.f.w vd, vs2, vm # Convert double-width float to single-width float. vfncvt.rod.f.f.w vd, vs2, vm # Convert double-width float to single-width float, # rounding towards odd.

ISA: v

", "tooltip": "vfncvt.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer. vfncvt.x.f.w vd, vs2, vm # Convert double-width float to signed integer. vfncvt.rtz.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer, truncating. vfncvt.rtz.x.f.w vd, vs2, vm # Convert double-width float to signed integer, truncating. vfncvt.f.xu.w vd, vs2, vm # Convert double-width unsigned integer to float. vfncvt.f.x.w vd, vs2, vm # Convert double-width signed integer to float. vfncvt.f.f.w vd, vs2, vm # Convert double-width float to single-width float. vfncvt.rod.f.f.w vd, vs2, vm # Convert double-width float to single-width float, # rounding towards odd.\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_narrowing_floating_pointinteger_type_convert_instructions" }; case "VFNCVT.F.X.W": return { "html": "

VFNCVT.F.X.W vs2, vd

vfncvt.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer. vfncvt.x.f.w vd, vs2, vm # Convert double-width float to signed integer. vfncvt.rtz.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer, truncating. vfncvt.rtz.x.f.w vd, vs2, vm # Convert double-width float to signed integer, truncating. vfncvt.f.xu.w vd, vs2, vm # Convert double-width unsigned integer to float. vfncvt.f.x.w vd, vs2, vm # Convert double-width signed integer to float. vfncvt.f.f.w vd, vs2, vm # Convert double-width float to single-width float. vfncvt.rod.f.f.w vd, vs2, vm # Convert double-width float to single-width float, # rounding towards odd.

ISA: v

VFNCVT.F.XU.W vs2, vd

vfncvt.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer. vfncvt.x.f.w vd, vs2, vm # Convert double-width float to signed integer. vfncvt.rtz.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer, truncating. vfncvt.rtz.x.f.w vd, vs2, vm # Convert double-width float to signed integer, truncating. vfncvt.f.xu.w vd, vs2, vm # Convert double-width unsigned integer to float. vfncvt.f.x.w vd, vs2, vm # Convert double-width signed integer to float. vfncvt.f.f.w vd, vs2, vm # Convert double-width float to single-width float. vfncvt.rod.f.f.w vd, vs2, vm # Convert double-width float to single-width float, # rounding towards odd.

ISA: v

VFNCVT.ROD.F.F.W vs2, vd

vfncvt.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer. vfncvt.x.f.w vd, vs2, vm # Convert double-width float to signed integer. vfncvt.rtz.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer, truncating. vfncvt.rtz.x.f.w vd, vs2, vm # Convert double-width float to signed integer, truncating. vfncvt.f.xu.w vd, vs2, vm # Convert double-width unsigned integer to float. vfncvt.f.x.w vd, vs2, vm # Convert double-width signed integer to float. vfncvt.f.f.w vd, vs2, vm # Convert double-width float to single-width float. vfncvt.rod.f.f.w vd, vs2, vm # Convert double-width float to single-width float, # rounding towards odd.

ISA: v

VFNCVT.RTZ.X.F.W vs2, vd

vfncvt.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer. vfncvt.x.f.w vd, vs2, vm # Convert double-width float to signed integer. vfncvt.rtz.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer, truncating. vfncvt.rtz.x.f.w vd, vs2, vm # Convert double-width float to signed integer, truncating. vfncvt.f.xu.w vd, vs2, vm # Convert double-width unsigned integer to float. vfncvt.f.x.w vd, vs2, vm # Convert double-width signed integer to float. vfncvt.f.f.w vd, vs2, vm # Convert double-width float to single-width float. vfncvt.rod.f.f.w vd, vs2, vm # Convert double-width float to single-width float, # rounding towards odd.

ISA: v

VFNCVT.RTZ.XU.F.W vs2, vd

vfncvt.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer. vfncvt.x.f.w vd, vs2, vm # Convert double-width float to signed integer. vfncvt.rtz.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer, truncating. vfncvt.rtz.x.f.w vd, vs2, vm # Convert double-width float to signed integer, truncating. vfncvt.f.xu.w vd, vs2, vm # Convert double-width unsigned integer to float. vfncvt.f.x.w vd, vs2, vm # Convert double-width signed integer to float. vfncvt.f.f.w vd, vs2, vm # Convert double-width float to single-width float. vfncvt.rod.f.f.w vd, vs2, vm # Convert double-width float to single-width float, # rounding towards odd.

ISA: v

VFNCVT.X.F.W vs2, vd

vfncvt.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer. vfncvt.x.f.w vd, vs2, vm # Convert double-width float to signed integer. vfncvt.rtz.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer, truncating. vfncvt.rtz.x.f.w vd, vs2, vm # Convert double-width float to signed integer, truncating. vfncvt.f.xu.w vd, vs2, vm # Convert double-width unsigned integer to float. vfncvt.f.x.w vd, vs2, vm # Convert double-width signed integer to float. vfncvt.f.f.w vd, vs2, vm # Convert double-width float to single-width float. vfncvt.rod.f.f.w vd, vs2, vm # Convert double-width float to single-width float, # rounding towards odd.

ISA: v

VFNCVT.XU.F.W vs2, vd

vfncvt.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer. vfncvt.x.f.w vd, vs2, vm # Convert double-width float to signed integer. vfncvt.rtz.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer, truncating. vfncvt.rtz.x.f.w vd, vs2, vm # Convert double-width float to signed integer, truncating. vfncvt.f.xu.w vd, vs2, vm # Convert double-width unsigned integer to float. vfncvt.f.x.w vd, vs2, vm # Convert double-width signed integer to float. vfncvt.f.f.w vd, vs2, vm # Convert double-width float to single-width float. vfncvt.rod.f.f.w vd, vs2, vm # Convert double-width float to single-width float, # rounding towards odd.

ISA: v

VFNMACC.VF vs2, rs1, vd

vfnmacc

ISA: v

", "tooltip": "vfnmacc\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFNMACC.VV": return { "html": "

VFNMACC.VV vs2, vs1, vd

vfnmacc

ISA: v

", "tooltip": "vfnmacc\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFNMADD.VF": return { "html": "

VFNMADD.VF vs2, rs1, vd

vfnmadd

ISA: v

", "tooltip": "vfnmadd\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFNMADD.VV": return { "html": "

VFNMADD.VV vs2, vs1, vd

vfnmadd

ISA: v

", "tooltip": "vfnmadd\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFNMSAC.VF": return { "html": "

VFNMSAC.VF vs2, rs1, vd

vfnmsac

ISA: v

", "tooltip": "vfnmsac\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFNMSAC.VV": return { "html": "

VFNMSAC.VV vs2, vs1, vd

vfnmsac

ISA: v

", "tooltip": "vfnmsac\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFNMSUB.VF": return { "html": "

VFNMSUB.VF vs2, rs1, vd

vfnmsub

ISA: v

", "tooltip": "vfnmsub\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFNMSUB.VV": return { "html": "

VFNMSUB.VV vs2, vs1, vd

vfnmsub

ISA: v

", "tooltip": "vfnmsub\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFRDIV.VF": return { "html": "

VFRDIV.VF vs2, rs1, vd

vfrdiv

ISA: v

", "tooltip": "vfrdiv\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFREC7.V": return { "html": "

VFREC7.V vs2, vd

Table 17. vfrec7.v common-case lookup table contents
# Floating-point reciprocal estimate to 7 bits. vfrec7.v vd, vs2, vm

ISA: v

", "tooltip": "Table 17. vfrec7.v common-case lookup table contents\n# Floating-point reciprocal estimate to 7 bits. vfrec7.v vd, vs2, vm\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_floating_point_reciprocal_estimate_instruction" }; case "VFREDMAX.VS": return { "html": "

VFREDMAX.VS vs2, vs1, vd

vfredmax

ISA: v

", "tooltip": "vfredmax\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFREDMIN.VS": return { "html": "

VFREDMIN.VS vs2, vs1, vd

vfredmin

ISA: v

", "tooltip": "vfredmin\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFREDOSUM.VS": return { "html": "

VFREDOSUM.VS vs2, vs1, vd

# Simple reductions. vfredosum.vs vd, vs2, vs1, vm # Ordered sum vfredusum.vs vd, vs2, vs1, vm # Unordered sum vfredmax.vs vd, vs2, vs1, vm # Maximum value vfredmin.vs vd, vs2, vs1, vm # Minimum value

ISA: v

", "tooltip": "# Simple reductions. vfredosum.vs vd, vs2, vs1, vm # Ordered sum vfredusum.vs vd, vs2, vs1, vm # Unordered sum vfredmax.vs vd, vs2, vs1, vm # Maximum value vfredmin.vs vd, vs2, vs1, vm # Minimum value\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#sec-vector-float-reduce" }; case "VFREDSUM.VS": return { "html": "

VFREDSUM.VS vs2, vs1, vd

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VFREDUSUM.VS": return { "html": "

VFREDUSUM.VS vs2, vs1, vd

The unordered sum reduction instruction, vfredusum, provides an implementation more freedom in performing the reduction.

ISA: v

", "tooltip": "The unordered sum reduction instruction, vfredusum, provides an implementation more freedom in performing the reduction.\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_unordered_single_width_floating_point_sum_reduction" }; case "VFRSQRT7.V": return { "html": "

VFRSQRT7.V vs2, vd

Table 16. vfrsqrt7.v common-case lookup table contents
# Floating-point reciprocal square-root estimate to 7 bits. vfrsqrt7.v vd, vs2, vm

ISA: v

", "tooltip": "Table 16. vfrsqrt7.v common-case lookup table contents\n# Floating-point reciprocal square-root estimate to 7 bits. vfrsqrt7.v vd, vs2, vm\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_floating_point_reciprocal_square_root_estimate_instruction" }; case "VFRSUB.VF": return { "html": "

VFRSUB.VF vs2, rs1, vd

vfrsub

ISA: v

", "tooltip": "vfrsub\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFSGNJ.VF": return { "html": "

VFSGNJ.VF vs2, rs1, vd

vfsgnj.vv vd, vs2, vs1, vm # Vector-vector vfsgnj.vf vd, vs2, rs1, vm # vector-scalar vfsgnjn.vv vd, vs2, vs1, vm # Vector-vector vfsgnjn.vf vd, vs2, rs1, vm # vector-scalar vfsgnjx.vv vd, vs2, vs1, vm # Vector-vector vfsgnjx.vf vd, vs2, rs1, vm # vector-scalar

ISA: v

", "tooltip": "vfsgnj.vv vd, vs2, vs1, vm # Vector-vector vfsgnj.vf vd, vs2, rs1, vm # vector-scalar vfsgnjn.vv vd, vs2, vs1, vm # Vector-vector vfsgnjn.vf vd, vs2, rs1, vm # vector-scalar vfsgnjx.vv vd, vs2, vs1, vm # Vector-vector vfsgnjx.vf vd, vs2, rs1, vm # vector-scalar\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_floating_point_sign_injection_instructions" }; case "VFSGNJ.VV": return { "html": "

VFSGNJ.VV vs2, vs1, vd

vfsgnj.vv vd, vs2, vs1, vm # Vector-vector vfsgnj.vf vd, vs2, rs1, vm # vector-scalar vfsgnjn.vv vd, vs2, vs1, vm # Vector-vector vfsgnjn.vf vd, vs2, rs1, vm # vector-scalar vfsgnjx.vv vd, vs2, vs1, vm # Vector-vector vfsgnjx.vf vd, vs2, rs1, vm # vector-scalar

ISA: v

VFSGNJN.VF vs2, rs1, vd

vfsgnjn

ISA: v

", "tooltip": "vfsgnjn\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFSGNJN.VV": return { "html": "

VFSGNJN.VV vs2, vs1, vd

vfsgnjn

ISA: v

", "tooltip": "vfsgnjn\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFSGNJX.VF": return { "html": "

VFSGNJX.VF vs2, rs1, vd

vfsgnjx

ISA: v

", "tooltip": "vfsgnjx\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFSGNJX.VV": return { "html": "

VFSGNJX.VV vs2, vs1, vd

vfsgnjx

ISA: v

", "tooltip": "vfsgnjx\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFSLIDE1DOWN.VF": return { "html": "

VFSLIDE1DOWN.VF vs2, rs1, vd

The vfslide1down instruction is defined analogously, but sources its scalar argument from an f register.

ISA: v

", "tooltip": "The vfslide1down instruction is defined analogously, but sources its scalar argument from an f register.\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_slide1down_instruction" }; case "VFSLIDE1UP.VF": return { "html": "

VFSLIDE1UP.VF vs2, rs1, vd

The vfslide1up instruction is defined analogously, but sources its scalar argument from an f register.

ISA: v

", "tooltip": "The vfslide1up instruction is defined analogously, but sources its scalar argument from an f register.\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_slide1up" }; case "VFSQRT.V": return { "html": "

VFSQRT.V vs2, vd

# Floating-point square root vfsqrt.v vd, vs2, vm # Vector-vector square root

ISA: v

", "tooltip": "# Floating-point square root vfsqrt.v vd, vs2, vm # Vector-vector square root\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_floating_point_square_root_instruction" }; case "VFSUB.VF": return { "html": "

VFSUB.VF vs2, rs1, vd

vfsub

ISA: v

", "tooltip": "vfsub\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFSUB.VV": return { "html": "

VFSUB.VV vs2, vs1, vd

vfsub

ISA: v

", "tooltip": "vfsub\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFWADD.VF": return { "html": "

VFWADD.VF vs2, rs1, vd

# Widening FP add/subtract, 2*SEW = SEW +/- SEW vfwadd.vv vd, vs2, vs1, vm # vector-vector vfwadd.vf vd, vs2, rs1, vm # vector-scalar vfwsub.vv vd, vs2, vs1, vm # vector-vector vfwsub.vf vd, vs2, rs1, vm # vector-scalar # Widening FP add/subtract, 2*SEW = 2*SEW +/- SEW vfwadd.wv vd, vs2, vs1, vm # vector-vector vfwadd.wf vd, vs2, rs1, vm # vector-scalar vfwsub.wv vd, vs2, vs1, vm # vector-vector vfwsub.wf vd, vs2, rs1, vm # vector-scalar

ISA: v

", "tooltip": "# Widening FP add/subtract, 2*SEW = SEW +/- SEW vfwadd.vv vd, vs2, vs1, vm # vector-vector vfwadd.vf vd, vs2, rs1, vm # vector-scalar vfwsub.vv vd, vs2, vs1, vm # vector-vector vfwsub.vf vd, vs2, rs1, vm # vector-scalar # Widening FP add/subtract, 2*SEW = 2*SEW +/- SEW vfwadd.wv vd, vs2, vs1, vm # vector-vector vfwadd.wf vd, vs2, rs1, vm # vector-scalar vfwsub.wv vd, vs2, vs1, vm # vector-vector vfwsub.wf vd, vs2, rs1, vm # vector-scalar\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_widening_floating_point_addsubtract_instructions" }; case "VFWADD.VV": return { "html": "

VFWADD.VV vs2, vs1, vd

# Widening FP add/subtract, 2*SEW = SEW +/- SEW vfwadd.vv vd, vs2, vs1, vm # vector-vector vfwadd.vf vd, vs2, rs1, vm # vector-scalar vfwsub.vv vd, vs2, vs1, vm # vector-vector vfwsub.vf vd, vs2, rs1, vm # vector-scalar # Widening FP add/subtract, 2*SEW = 2*SEW +/- SEW vfwadd.wv vd, vs2, vs1, vm # vector-vector vfwadd.wf vd, vs2, rs1, vm # vector-scalar vfwsub.wv vd, vs2, vs1, vm # vector-vector vfwsub.wf vd, vs2, rs1, vm # vector-scalar

ISA: v

VFWADD.WF vs2, rs1, vd

# Widening FP add/subtract, 2*SEW = SEW +/- SEW vfwadd.vv vd, vs2, vs1, vm # vector-vector vfwadd.vf vd, vs2, rs1, vm # vector-scalar vfwsub.vv vd, vs2, vs1, vm # vector-vector vfwsub.vf vd, vs2, rs1, vm # vector-scalar # Widening FP add/subtract, 2*SEW = 2*SEW +/- SEW vfwadd.wv vd, vs2, vs1, vm # vector-vector vfwadd.wf vd, vs2, rs1, vm # vector-scalar vfwsub.wv vd, vs2, vs1, vm # vector-vector vfwsub.wf vd, vs2, rs1, vm # vector-scalar

ISA: v

VFWADD.WV vs2, vs1, vd

# Widening FP add/subtract, 2*SEW = SEW +/- SEW vfwadd.vv vd, vs2, vs1, vm # vector-vector vfwadd.vf vd, vs2, rs1, vm # vector-scalar vfwsub.vv vd, vs2, vs1, vm # vector-vector vfwsub.vf vd, vs2, rs1, vm # vector-scalar # Widening FP add/subtract, 2*SEW = 2*SEW +/- SEW vfwadd.wv vd, vs2, vs1, vm # vector-vector vfwadd.wf vd, vs2, rs1, vm # vector-scalar vfwsub.wv vd, vs2, vs1, vm # vector-vector vfwsub.wf vd, vs2, rs1, vm # vector-scalar

ISA: v

VFWCVT.F.F.V vs2, vd

vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer. vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer. vfwcvt.rtz.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer, truncating. vfwcvt.rtz.x.f.v vd, vs2, vm # Convert float to double-width signed integer, truncating. vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float. vfwcvt.f.x.v vd, vs2, vm # Convert signed integer to double-width float. vfwcvt.f.f.v vd, vs2, vm # Convert single-width float to double-width float.

ISA: v

", "tooltip": "vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer. vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer. vfwcvt.rtz.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer, truncating. vfwcvt.rtz.x.f.v vd, vs2, vm # Convert float to double-width signed integer, truncating. vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float. vfwcvt.f.x.v vd, vs2, vm # Convert signed integer to double-width float. vfwcvt.f.f.v vd, vs2, vm # Convert single-width float to double-width float.\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_widening_floating_pointinteger_type_convert_instructions" }; case "VFWCVT.F.X.V": return { "html": "

VFWCVT.F.X.V vs2, vd

vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer. vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer. vfwcvt.rtz.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer, truncating. vfwcvt.rtz.x.f.v vd, vs2, vm # Convert float to double-width signed integer, truncating. vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float. vfwcvt.f.x.v vd, vs2, vm # Convert signed integer to double-width float. vfwcvt.f.f.v vd, vs2, vm # Convert single-width float to double-width float.

ISA: v

VFWCVT.F.XU.V vs2, vd

vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer. vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer. vfwcvt.rtz.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer, truncating. vfwcvt.rtz.x.f.v vd, vs2, vm # Convert float to double-width signed integer, truncating. vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float. vfwcvt.f.x.v vd, vs2, vm # Convert signed integer to double-width float. vfwcvt.f.f.v vd, vs2, vm # Convert single-width float to double-width float.

ISA: v

VFWCVT.RTZ.X.F.V vs2, vd

vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer. vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer. vfwcvt.rtz.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer, truncating. vfwcvt.rtz.x.f.v vd, vs2, vm # Convert float to double-width signed integer, truncating. vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float. vfwcvt.f.x.v vd, vs2, vm # Convert signed integer to double-width float. vfwcvt.f.f.v vd, vs2, vm # Convert single-width float to double-width float.

ISA: v

VFWCVT.RTZ.XU.F.V vs2, vd

vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer. vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer. vfwcvt.rtz.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer, truncating. vfwcvt.rtz.x.f.v vd, vs2, vm # Convert float to double-width signed integer, truncating. vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float. vfwcvt.f.x.v vd, vs2, vm # Convert signed integer to double-width float. vfwcvt.f.f.v vd, vs2, vm # Convert single-width float to double-width float.

ISA: v

VFWCVT.X.F.V vs2, vd

vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer. vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer. vfwcvt.rtz.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer, truncating. vfwcvt.rtz.x.f.v vd, vs2, vm # Convert float to double-width signed integer, truncating. vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float. vfwcvt.f.x.v vd, vs2, vm # Convert signed integer to double-width float. vfwcvt.f.f.v vd, vs2, vm # Convert single-width float to double-width float.

ISA: v

VFWCVT.XU.F.V vs2, vd

vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer. vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer. vfwcvt.rtz.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer, truncating. vfwcvt.rtz.x.f.v vd, vs2, vm # Convert float to double-width signed integer, truncating. vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float. vfwcvt.f.x.v vd, vs2, vm # Convert signed integer to double-width float. vfwcvt.f.f.v vd, vs2, vm # Convert single-width float to double-width float.

ISA: v

VFWMACC.VF vs2, rs1, vd

# FP widening multiply-accumulate, overwrites addend vfwmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vfwmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i] # FP widening negate-(multiply-accumulate), overwrites addend vfwnmacc.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) - vd[i] vfwnmacc.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) - vd[i] # FP widening multiply-subtract-accumulator, overwrites addend vfwmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) - vd[i] vfwmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) - vd[i] # FP widening negate-(multiply-subtract-accumulator), overwrites addend vfwnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] vfwnmsac.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) + vd[i]

ISA: v

", "tooltip": "# FP widening multiply-accumulate, overwrites addend vfwmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vfwmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i] # FP widening negate-(multiply-accumulate), overwrites addend vfwnmacc.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) - vd[i] vfwnmacc.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) - vd[i] # FP widening multiply-subtract-accumulator, overwrites addend vfwmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) - vd[i] vfwmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) - vd[i] # FP widening negate-(multiply-subtract-accumulator), overwrites addend vfwnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] vfwnmsac.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) + vd[i]\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_widening_floating_point_fused_multiply_add_instructions" }; case "VFWMACC.VV": return { "html": "

VFWMACC.VV vs2, vs1, vd

# FP widening multiply-accumulate, overwrites addend vfwmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vfwmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i] # FP widening negate-(multiply-accumulate), overwrites addend vfwnmacc.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) - vd[i] vfwnmacc.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) - vd[i] # FP widening multiply-subtract-accumulator, overwrites addend vfwmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) - vd[i] vfwmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) - vd[i] # FP widening negate-(multiply-subtract-accumulator), overwrites addend vfwnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] vfwnmsac.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) + vd[i]

ISA: v

VFWMSAC.VF vs2, rs1, vd

vfwmsac

ISA: v

", "tooltip": "vfwmsac\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFWMSAC.VV": return { "html": "

VFWMSAC.VV vs2, vs1, vd

vfwmsac

ISA: v

", "tooltip": "vfwmsac\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFWMUL.VF": return { "html": "

VFWMUL.VF vs2, rs1, vd

# Widening floating-point multiply vfwmul.vv vd, vs2, vs1, vm # vector-vector vfwmul.vf vd, vs2, rs1, vm # vector-scalar

ISA: v

", "tooltip": "# Widening floating-point multiply vfwmul.vv vd, vs2, vs1, vm # vector-vector vfwmul.vf vd, vs2, rs1, vm # vector-scalar\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_widening_floating_point_multiply" }; case "VFWMUL.VV": return { "html": "

VFWMUL.VV vs2, vs1, vd

# Widening floating-point multiply vfwmul.vv vd, vs2, vs1, vm # vector-vector vfwmul.vf vd, vs2, rs1, vm # vector-scalar

ISA: v

VFWNMACC.VF vs2, rs1, vd

vfwnmacc

ISA: v

", "tooltip": "vfwnmacc\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFWNMACC.VV": return { "html": "

VFWNMACC.VV vs2, vs1, vd

vfwnmacc

ISA: v

VFWNMSAC.VF vs2, rs1, vd

vfwnmsac

ISA: v

", "tooltip": "vfwnmsac\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFWNMSAC.VV": return { "html": "

VFWNMSAC.VV vs2, vs1, vd

vfwnmsac

ISA: v

VFWREDOSUM.VS vs2, vs1, vd

# Simple reductions. vfwredosum.vs vd, vs2, vs1, vm # Ordered sum vfwredusum.vs vd, vs2, vs1, vm # Unordered sum

ISA: v

", "tooltip": "# Simple reductions. vfwredosum.vs vd, vs2, vs1, vm # Ordered sum vfwredusum.vs vd, vs2, vs1, vm # Unordered sum\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#sec-vector-float-reduce-widen" }; case "VFWREDSUM.VS": return { "html": "

VFWREDSUM.VS vs2, vs1, vd

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VFWREDUSUM.VS": return { "html": "

VFWREDUSUM.VS vs2, vs1, vd

vfwredusum

ISA: v

", "tooltip": "vfwredusum\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFWSUB.VF": return { "html": "

VFWSUB.VF vs2, rs1, vd

vfwsub
vfwsub.w

ISA: v

", "tooltip": "vfwsub\nvfwsub.w\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VFWSUB.VV": return { "html": "

VFWSUB.VV vs2, vs1, vd

vfwsub
vfwsub.w

ISA: v

VFWSUB.WF vs2, rs1, vd

vfwsub
vfwsub.w

ISA: v

VFWSUB.WV vs2, vs1, vd

vfwsub
vfwsub.w

ISA: v

VID.V vd

The vid.v instruction writes each element's index to the destination vector register group, from 0 to vl-1.
vid.v vd, vm # Write element ID to destination.

ISA: v

", "tooltip": "The vid.v instruction writes each element's index to the destination vector register group, from 0 to vl-1.\nvid.v vd, vm # Write element ID to destination.\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_element_index_instruction" }; case "VIOTA.M": return { "html": "

VIOTA.M vs2, vd

The viota.m instruction reads a source vector mask register and writes to each element of the destination vector register group the sum of all the bits of elements in the mask register whose index is less than the element, e.g., a parallel prefix sum of the mask values.
Traps on viota.m are always reported with a vstart of 0, and execution is always restarted from the beginning when resuming after a trap handler. An illegal instruction exception is raised if vstart is non-zero.
The viota.m instruction can be combined with memory scatter instructions (indexed stores) to perform vector compress functions.
viota.m vd, vs2, vm # Example 7 6 5 4 3 2 1 0 Element number 1 0 0 1 0 0 0 1 v2 contents viota.m v4, v2 # Unmasked 2 2 2 1 1 1 1 0 v4 result 1 1 1 0 1 0 1 1 v0 contents 1 0 0 1 0 0 0 1 v2 contents 2 3 4 5 6 7 8 9 v4 contents viota.m v4, v2, v0.t # Masked, vtype.vma=0 1 1 1 5 1 7 1 0 v4 results

ISA: v

", "tooltip": "The viota.m instruction reads a source vector mask register and writes to each element of the destination vector register group the sum of all the bits of elements in the mask register whose index is less than the element, e.g., a parallel prefix sum of the mask values.\nTraps on viota.m are always reported with a vstart of 0, and execution is always restarted from the beginning when resuming after a trap handler. An illegal instruction exception is raised if vstart is non-zero.\nThe viota.m instruction can be combined with memory scatter instructions (indexed stores) to perform vector compress functions.\nviota.m vd, vs2, vm # Example 7 6 5 4 3 2 1 0 Element number 1 0 0 1 0 0 0 1 v2 contents viota.m v4, v2 # Unmasked 2 2 2 1 1 1 1 0 v4 result 1 1 1 0 1 0 1 1 v0 contents 1 0 0 1 0 0 0 1 v2 contents 2 3 4 5 6 7 8 9 v4 contents viota.m v4, v2, v0.t # Masked, vtype.vma=0 1 1 1 5 1 7 1 0 v4 results\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_iota_instruction" }; case "VL1R.V": return { "html": "

VL1R.V rs1, vd

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VL1RE16.V": return { "html": "

VL1RE16.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VL1RE32.V": return { "html": "

VL1RE32.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VL1RE64.V": return { "html": "

VL1RE64.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VL1RE8.V": return { "html": "

VL1RE8.V rs1, vd

# Format of whole register load and store instructions. vl1r.v v3, (a0) # Pseudoinstruction equal to vl1re8.v vl1re8.v v3, (a0) # Load v3 with VLEN/8 bytes held at address in a0 vl1re16.v v3, (a0) # Load v3 with VLEN/16 halfwords held at address in a0 vl1re32.v v3, (a0) # Load v3 with VLEN/32 words held at address in a0 vl1re64.v v3, (a0) # Load v3 with VLEN/64 doublewords held at address in a0 vl2r.v v2, (a0) # Pseudoinstruction equal to vl2re8.v v2, (a0) vl2re8.v v2, (a0) # Load v2-v3 with 2*VLEN/8 bytes from address in a0 vl2re16.v v2, (a0) # Load v2-v3 with 2*VLEN/16 halfwords held at address in a0 vl2re32.v v2, (a0) # Load v2-v3 with 2*VLEN/32 words held at address in a0 vl2re64.v v2, (a0) # Load v2-v3 with 2*VLEN/64 doublewords held at address in a0 vl4r.v v4, (a0) # Pseudoinstruction equal to vl4re8.v vl4re8.v v4, (a0) # Load v4-v7 with 4*VLEN/8 bytes from address in a0 vl4re16.v v4, (a0) vl4re32.v v4, (a0) vl4re64.v v4, (a0) vl8r.v v8, (a0) # Pseudoinstruction equal to vl8re8.v vl8re8.v v8, (a0) # Load v8-v15 with 8*VLEN/8 bytes from address in a0 vl8re16.v v8, (a0) vl8re32.v v8, (a0) vl8re64.v v8, (a0) vs1r.v v3, (a1) # Store v3 to address in a1 vs2r.v v2, (a1) # Store v2-v3 to address in a1 vs4r.v v4, (a1) # Store v4-v7 to address in a1 vs8r.v v8, (a1) # Store v8-v15 to address in a1

ISA: v

", "tooltip": "# Format of whole register load and store instructions. vl1r.v v3, (a0) # Pseudoinstruction equal to vl1re8.v vl1re8.v v3, (a0) # Load v3 with VLEN/8 bytes held at address in a0 vl1re16.v v3, (a0) # Load v3 with VLEN/16 halfwords held at address in a0 vl1re32.v v3, (a0) # Load v3 with VLEN/32 words held at address in a0 vl1re64.v v3, (a0) # Load v3 with VLEN/64 doublewords held at address in a0 vl2r.v v2, (a0) # Pseudoinstruction equal to vl2re8.v v2, (a0) vl2re8.v v2, (a0) # Load v2-v3 with 2*VLEN/8 bytes from address in a0 vl2re16.v v2, (a0) # Load v2-v3 with 2*VLEN/16 halfwords held at address in a0 vl2re32.v v2, (a0) # Load v2-v3 with 2*VLEN/32 words held at address in a0 vl2re64.v v2, (a0) # Load v2-v3 with 2*VLEN/64 doublewords held at address in a0 vl4r.v v4, (a0) # Pseudoinstruction equal to vl4re8.v vl4re8.v v4, (a0) # Load v4-v7 with 4*VLEN/8 bytes from address in a0 vl4re16.v v4, (a0) vl4re32.v v4, (a0) vl4re64.v v4, (a0) vl8r.v v8, (a0) # Pseudoinstruction equal to vl8re8.v vl8re8.v v8, (a0) # Load v8-v15 with 8*VLEN/8 bytes from address in a0 vl8re16.v v8, (a0) vl8re32.v v8, (a0) vl8re64.v v8, (a0) vs1r.v v3, (a1) # Store v3 to address in a1 vs2r.v v2, (a1) # Store v2-v3 to address in a1 vs4r.v v4, (a1) # Store v4-v7 to address in a1 vs8r.v v8, (a1) # Store v8-v15 to address in a1\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_loadstore_whole_register_instructions" }; case "VL2R.V": return { "html": "

VL2R.V rs1, vd

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VL2RE16.V": return { "html": "

VL2RE16.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VL2RE32.V": return { "html": "

VL2RE32.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VL2RE64.V": return { "html": "

VL2RE64.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VL2RE8.V": return { "html": "

VL2RE8.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VL4R.V": return { "html": "

VL4R.V rs1, vd

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VL4RE16.V": return { "html": "

VL4RE16.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VL4RE32.V": return { "html": "

VL4RE32.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VL4RE64.V": return { "html": "

VL4RE64.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VL4RE8.V": return { "html": "

VL4RE8.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VL8R.V": return { "html": "

VL8R.V rs1, vd

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VL8RE16.V": return { "html": "

VL8RE16.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VL8RE32.V": return { "html": "

VL8RE32.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VL8RE64.V": return { "html": "

VL8RE64.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VL8RE8.V": return { "html": "

VL8RE8.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLE1.V": return { "html": "

VLE1.V rs1, vd

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLE1024.V": return { "html": "

VLE1024.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLE1024FF.V": return { "html": "

VLE1024FF.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLE128.V": return { "html": "

VLE128.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLE128FF.V": return { "html": "

VLE128FF.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLE16.V": return { "html": "

VLE16.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLE16FF.V": return { "html": "

VLE16FF.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLE256.V": return { "html": "

VLE256.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLE256FF.V": return { "html": "

VLE256FF.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLE32.V": return { "html": "

VLE32.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLE32FF.V": return { "html": "

VLE32FF.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLE512.V": return { "html": "

VLE512.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLE512FF.V": return { "html": "

VLE512FF.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLE64.V": return { "html": "

VLE64.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLE64FF.V": return { "html": "

VLE64FF.V rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLE8.V": return { "html": "

VLE8.V rs1, vd

# Vector unit-stride loads and stores # vd destination, rs1 base address, vm is mask encoding (v0.t or ) vle8.v vd, (rs1), vm # 8-bit unit-stride load vle16.v vd, (rs1), vm # 16-bit unit-stride load vle32.v vd, (rs1), vm # 32-bit unit-stride load vle64.v vd, (rs1), vm # 64-bit unit-stride load # vs3 store data, rs1 base address, vm is mask encoding (v0.t or ) vse8.v vs3, (rs1), vm # 8-bit unit-stride store vse16.v vs3, (rs1), vm # 16-bit unit-stride store vse32.v vs3, (rs1), vm # 32-bit unit-stride store vse64.v vs3, (rs1), vm # 64-bit unit-stride store

ISA: v

", "tooltip": "# Vector unit-stride loads and stores # vd destination, rs1 base address, vm is mask encoding (v0.t or ) vle8.v vd, (rs1), vm # 8-bit unit-stride load vle16.v vd, (rs1), vm # 16-bit unit-stride load vle32.v vd, (rs1), vm # 32-bit unit-stride load vle64.v vd, (rs1), vm # 64-bit unit-stride load # vs3 store data, rs1 base address, vm is mask encoding (v0.t or ) vse8.v vs3, (rs1), vm # 8-bit unit-stride store vse16.v vs3, (rs1), vm # 16-bit unit-stride store vse32.v vs3, (rs1), vm # 32-bit unit-stride store vse64.v vs3, (rs1), vm # 64-bit unit-stride store\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_unit_stride_instructions" }; case "VLE8FF.V": return { "html": "

VLE8FF.V rs1, vd

# Vector unit-stride fault-only-first loads # vd destination, rs1 base address, vm is mask encoding (v0.t or ) vle8ff.v vd, (rs1), vm # 8-bit unit-stride fault-only-first load vle16ff.v vd, (rs1), vm # 16-bit unit-stride fault-only-first load vle32ff.v vd, (rs1), vm # 32-bit unit-stride fault-only-first load vle64ff.v vd, (rs1), vm # 64-bit unit-stride fault-only-first load

ISA: v

", "tooltip": "# Vector unit-stride fault-only-first loads # vd destination, rs1 base address, vm is mask encoding (v0.t or ) vle8ff.v vd, (rs1), vm # 8-bit unit-stride fault-only-first load vle16ff.v vd, (rs1), vm # 16-bit unit-stride fault-only-first load vle32ff.v vd, (rs1), vm # 32-bit unit-stride fault-only-first load vle64ff.v vd, (rs1), vm # 64-bit unit-stride fault-only-first load\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_unit_stride_fault_only_first_loads" }; case "VLM.V": return { "html": "

VLM.V rs1, vd

vlm.v and vsm.v are encoded with the same width[2:0]=0 encoding as vle8.v and vse8.v, but are distinguished by different lumop and sumop encodings. Since vlm.v and vsm.v operate as byte loads and stores, vstart is in units of bytes for these instructions.
# Vector unit-stride mask load vlm.v vd, (rs1) # Load byte vector of length ceil(vl/8) # Vector unit-stride mask store vsm.v vs3, (rs1) # Store byte vector of length ceil(vl/8)

ISA: v

", "tooltip": "vlm.v and vsm.v are encoded with the same width[2:0]=0 encoding as vle8.v and vse8.v, but are distinguished by different lumop and sumop encodings. Since vlm.v and vsm.v operate as byte loads and stores, vstart is in units of bytes for these instructions.\n# Vector unit-stride mask load vlm.v vd, (rs1) # Load byte vector of length ceil(vl/8) # Vector unit-stride mask store vsm.v vs3, (rs1) # Store byte vector of length ceil(vl/8)\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_unit_stride_instructions" }; case "VLOXEI1024.V": return { "html": "

VLOXEI1024.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLOXEI128.V": return { "html": "

VLOXEI128.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLOXEI16.V": return { "html": "

VLOXEI16.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLOXEI256.V": return { "html": "

VLOXEI256.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLOXEI32.V": return { "html": "

VLOXEI32.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLOXEI512.V": return { "html": "

VLOXEI512.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLOXEI64.V": return { "html": "

VLOXEI64.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLOXEI8.V": return { "html": "

VLOXEI8.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLSE1024.V": return { "html": "

VLSE1024.V rs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLSE128.V": return { "html": "

VLSE128.V rs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLSE16.V": return { "html": "

VLSE16.V rs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLSE256.V": return { "html": "

VLSE256.V rs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLSE32.V": return { "html": "

VLSE32.V rs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLSE512.V": return { "html": "

VLSE512.V rs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLSE64.V": return { "html": "

VLSE64.V rs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLSE8.V": return { "html": "

VLSE8.V rs2, rs1, vd

# Vector strided loads and stores # vd destination, rs1 base address, rs2 byte stride vlse8.v vd, (rs1), rs2, vm # 8-bit strided load vlse16.v vd, (rs1), rs2, vm # 16-bit strided load vlse32.v vd, (rs1), rs2, vm # 32-bit strided load vlse64.v vd, (rs1), rs2, vm # 64-bit strided load # vs3 store data, rs1 base address, rs2 byte stride vsse8.v vs3, (rs1), rs2, vm # 8-bit strided store vsse16.v vs3, (rs1), rs2, vm # 16-bit strided store vsse32.v vs3, (rs1), rs2, vm # 32-bit strided store vsse64.v vs3, (rs1), rs2, vm # 64-bit strided store

ISA: v

", "tooltip": "# Vector strided loads and stores # vd destination, rs1 base address, rs2 byte stride vlse8.v vd, (rs1), rs2, vm # 8-bit strided load vlse16.v vd, (rs1), rs2, vm # 16-bit strided load vlse32.v vd, (rs1), rs2, vm # 32-bit strided load vlse64.v vd, (rs1), rs2, vm # 64-bit strided load # vs3 store data, rs1 base address, rs2 byte stride vsse8.v vs3, (rs1), rs2, vm # 8-bit strided store vsse16.v vs3, (rs1), rs2, vm # 16-bit strided store vsse32.v vs3, (rs1), rs2, vm # 32-bit strided store vsse64.v vs3, (rs1), rs2, vm # 64-bit strided store\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_strided_instructions" }; case "VLUXEI1024.V": return { "html": "

VLUXEI1024.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLUXEI128.V": return { "html": "

VLUXEI128.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLUXEI16.V": return { "html": "

VLUXEI16.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLUXEI256.V": return { "html": "

VLUXEI256.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLUXEI32.V": return { "html": "

VLUXEI32.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLUXEI512.V": return { "html": "

VLUXEI512.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLUXEI64.V": return { "html": "

VLUXEI64.V vs2, rs1, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VLUXEI8.V": return { "html": "

VLUXEI8.V vs2, rs1, vd

# Vector indexed loads and stores # Vector indexed-unordered load instructions # vd destination, rs1 base address, vs2 byte offsets vluxei8.v vd, (rs1), vs2, vm # unordered 8-bit indexed load of SEW data vluxei16.v vd, (rs1), vs2, vm # unordered 16-bit indexed load of SEW data vluxei32.v vd, (rs1), vs2, vm # unordered 32-bit indexed load of SEW data vluxei64.v vd, (rs1), vs2, vm # unordered 64-bit indexed load of SEW data # Vector indexed-ordered load instructions # vd destination, rs1 base address, vs2 byte offsets vloxei8.v vd, (rs1), vs2, vm # ordered 8-bit indexed load of SEW data vloxei16.v vd, (rs1), vs2, vm # ordered 16-bit indexed load of SEW data vloxei32.v vd, (rs1), vs2, vm # ordered 32-bit indexed load of SEW data vloxei64.v vd, (rs1), vs2, vm # ordered 64-bit indexed load of SEW data # Vector indexed-unordered store instructions # vs3 store data, rs1 base address, vs2 byte offsets vsuxei8.v vs3, (rs1), vs2, vm # unordered 8-bit indexed store of SEW data vsuxei16.v vs3, (rs1), vs2, vm # unordered 16-bit indexed store of SEW data vsuxei32.v vs3, (rs1), vs2, vm # unordered 32-bit indexed store of SEW data vsuxei64.v vs3, (rs1), vs2, vm # unordered 64-bit indexed store of SEW data # Vector indexed-ordered store instructions # vs3 store data, rs1 base address, vs2 byte offsets vsoxei8.v vs3, (rs1), vs2, vm # ordered 8-bit indexed store of SEW data vsoxei16.v vs3, (rs1), vs2, vm # ordered 16-bit indexed store of SEW data vsoxei32.v vs3, (rs1), vs2, vm # ordered 32-bit indexed store of SEW data vsoxei64.v vs3, (rs1), vs2, vm # ordered 64-bit indexed store of SEW data

ISA: v

", "tooltip": "# Vector indexed loads and stores # Vector indexed-unordered load instructions # vd destination, rs1 base address, vs2 byte offsets vluxei8.v vd, (rs1), vs2, vm # unordered 8-bit indexed load of SEW data vluxei16.v vd, (rs1), vs2, vm # unordered 16-bit indexed load of SEW data vluxei32.v vd, (rs1), vs2, vm # unordered 32-bit indexed load of SEW data vluxei64.v vd, (rs1), vs2, vm # unordered 64-bit indexed load of SEW data # Vector indexed-ordered load instructions # vd destination, rs1 base address, vs2 byte offsets vloxei8.v vd, (rs1), vs2, vm # ordered 8-bit indexed load of SEW data vloxei16.v vd, (rs1), vs2, vm # ordered 16-bit indexed load of SEW data vloxei32.v vd, (rs1), vs2, vm # ordered 32-bit indexed load of SEW data vloxei64.v vd, (rs1), vs2, vm # ordered 64-bit indexed load of SEW data # Vector indexed-unordered store instructions # vs3 store data, rs1 base address, vs2 byte offsets vsuxei8.v vs3, (rs1), vs2, vm # unordered 8-bit indexed store of SEW data vsuxei16.v vs3, (rs1), vs2, vm # unordered 16-bit indexed store of SEW data vsuxei32.v vs3, (rs1), vs2, vm # unordered 32-bit indexed store of SEW data vsuxei64.v vs3, (rs1), vs2, vm # unordered 64-bit indexed store of SEW data # Vector indexed-ordered store instructions # vs3 store data, rs1 base address, vs2 byte offsets vsoxei8.v vs3, (rs1), vs2, vm # ordered 8-bit indexed store of SEW data vsoxei16.v vs3, (rs1), vs2, vm # ordered 16-bit indexed store of SEW data vsoxei32.v vs3, (rs1), vs2, vm # ordered 32-bit indexed store of SEW data vsoxei64.v vs3, (rs1), vs2, vm # ordered 64-bit indexed store of SEW data\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_indexed_instructions" }; case "VMACC.VV": return { "html": "

VMACC.VV vs2, vs1, vd

The integer multiply-add instructions are destructive and are provided in two forms, one that overwrites the addend or minuend (vmacc, vnmsac) and one that overwrites the first multiplicand (vmadd, vnmsub).
# Integer multiply-add, overwrite addend vmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] # Integer multiply-sub, overwrite minuend vnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] vnmsac.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vs2[i]) + vd[i] # Integer multiply-add, overwrite multiplicand vmadd.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vd[i]) + vs2[i] vmadd.vx vd, rs1, vs2, vm # vd[i] = (x[rs1] * vd[i]) + vs2[i] # Integer multiply-sub, overwrite multiplicand vnmsub.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) + vs2[i] vnmsub.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vd[i]) + vs2[i]

ISA: v

", "tooltip": "The integer multiply-add instructions are destructive and are provided in two forms, one that overwrites the addend or minuend (vmacc, vnmsac) and one that overwrites the first multiplicand (vmadd, vnmsub).\n# Integer multiply-add, overwrite addend vmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] # Integer multiply-sub, overwrite minuend vnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] vnmsac.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vs2[i]) + vd[i] # Integer multiply-add, overwrite multiplicand vmadd.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vd[i]) + vs2[i] vmadd.vx vd, rs1, vs2, vm # vd[i] = (x[rs1] * vd[i]) + vs2[i] # Integer multiply-sub, overwrite multiplicand vnmsub.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) + vs2[i] vnmsub.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vd[i]) + vs2[i]\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_single_width_integer_multiply_add_instructions" }; case "VMACC.VX": return { "html": "

VMACC.VX vs2, rs1, vd

The integer multiply-add instructions are destructive and are provided in two forms, one that overwrites the addend or minuend (vmacc, vnmsac) and one that overwrites the first multiplicand (vmadd, vnmsub).
# Integer multiply-add, overwrite addend vmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] # Integer multiply-sub, overwrite minuend vnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] vnmsac.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vs2[i]) + vd[i] # Integer multiply-add, overwrite multiplicand vmadd.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vd[i]) + vs2[i] vmadd.vx vd, rs1, vs2, vm # vd[i] = (x[rs1] * vd[i]) + vs2[i] # Integer multiply-sub, overwrite multiplicand vnmsub.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) + vs2[i] vnmsub.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vd[i]) + vs2[i]

ISA: v

VMADC.VI vs2, simm5, vd

vmadc and vmsbc add or subtract the source operands, optionally add the carry-in or subtract the borrow-in if masked (vm=0), and write the result back to mask register vd. If unmasked (vm=1), there is no carry-in or borrow-in. These instructions operate on and write back all body elements, even if masked. Because these instructions produce a mask value, they always operate with a tail-agnostic policy.
# Example multi-word arithmetic sequence, accumulating into v4 vmadc.vvm v1, v4, v8, v0 # Get carry into temp register v1 vadc.vvm v4, v4, v8, v0 # Calc new sum vmmv.m v0, v1 # Move temp carry into v0 for next word

ISA: v

", "tooltip": "vmadc and vmsbc add or subtract the source operands, optionally add the carry-in or subtract the borrow-in if masked (vm=0), and write the result back to mask register vd. If unmasked (vm=1), there is no carry-in or borrow-in. These instructions operate on and write back all body elements, even if masked. Because these instructions produce a mask value, they always operate with a tail-agnostic policy.\n# Example multi-word arithmetic sequence, accumulating into v4 vmadc.vvm v1, v4, v8, v0 # Get carry into temp register v1 vadc.vvm v4, v4, v8, v0 # Calc new sum vmmv.m v0, v1 # Move temp carry into v0 for next word\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_integer_add_with_carry_subtract_with_borrow_instructions" }; case "VMADC.VIM": return { "html": "

VMADC.VIM vs2, simm5, vd

ISA: v

VMADC.VV vs2, vs1, vd

ISA: v

VMADC.VVM vs2, vs1, vd

vmadc and vmsbc add or subtract the source operands, optionally add the carry-in or subtract the borrow-in if masked (vm=0), and write the result back to mask register vd. If unmasked (vm=1), there is no carry-in or borrow-in. These instructions operate on and write back all body elements, even if masked. Because these instructions produce a mask value, they always operate with a tail-agnostic policy.
# Example multi-word arithmetic sequence, accumulating into v4 vmadc.vvm v1, v4, v8, v0 # Get carry into temp register v1 vadc.vvm v4, v4, v8, v0 # Calc new sum vmmv.m v0, v1 # Move temp carry into v0 for next word

ISA: v

VMADC.VX vs2, rs1, vd

ISA: v

VMADC.VXM vs2, rs1, vd

ISA: v

VMADD.VV vs2, vs1, vd

vmadd

ISA: v

", "tooltip": "vmadd\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMADD.VX": return { "html": "

VMADD.VX vs2, rs1, vd

vmadd

ISA: v

", "tooltip": "vmadd\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMAND.MM": return { "html": "

VMAND.MM vs2, vs1, vd

vmand.mm vd, src1, src2
vmand.mm vd, src2, src2
vmand.mm vd, src1, src1
vmand.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && vs1.mask[i] vmnand.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] && vs1.mask[i]) vmandn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && !vs1.mask[i] vmxor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] ^^ vs1.mask[i] vmor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || vs1.mask[i] vmnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] || vs1.mask[i]) vmorn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || !vs1.mask[i] vmxnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] ^^ vs1.mask[i])
vmmv.m vd, vs => vmand.mm vd, vs, vs # Copy mask register vmclr.m vd => vmxor.mm vd, vd, vd # Clear mask register vmset.m vd => vmxnor.mm vd, vd, vd # Set mask register vmnot.m vd, vs => vmnand.mm vd, vs, vs # Invert bits

ISA: v

", "tooltip": "vmand.mm vd, src1, src2\nvmand.mm vd, src2, src2\nvmand.mm vd, src1, src1\nvmand.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && vs1.mask[i] vmnand.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] && vs1.mask[i]) vmandn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && !vs1.mask[i] vmxor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] ^^ vs1.mask[i] vmor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || vs1.mask[i] vmnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] || vs1.mask[i]) vmorn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || !vs1.mask[i] vmxnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] ^^ vs1.mask[i])\nvmmv.m vd, vs => vmand.mm vd, vs, vs # Copy mask register vmclr.m vd => vmxor.mm vd, vd, vd # Clear mask register vmset.m vd => vmxnor.mm vd, vd, vd # Set mask register vmnot.m vd, vs => vmnand.mm vd, vs, vs # Invert bits\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#sec-mask-register-logical" }; case "VMANDN.MM": return { "html": "

VMANDN.MM vs2, vs1, vd

vmandn.mm vd, src2, src1
vmandn.mm vd, src1, src2

ISA: v

", "tooltip": "vmandn.mm vd, src2, src1\nvmandn.mm vd, src1, src2\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#sec-mask-register-logical" }; case "VMANDNOT.MM": return { "html": "

VMANDNOT.MM vs2, vs1, vd

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VMAX.VV": return { "html": "

VMAX.VV vs2, vs1, vd

vmax

ISA: v

", "tooltip": "vmax\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMAX.VX": return { "html": "

VMAX.VX vs2, rs1, vd

vmax

ISA: v

", "tooltip": "vmax\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMAXU.VV": return { "html": "

VMAXU.VV vs2, vs1, vd

vmaxu

ISA: v

", "tooltip": "vmaxu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMAXU.VX": return { "html": "

VMAXU.VX vs2, rs1, vd

vmaxu

ISA: v

", "tooltip": "vmaxu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMERGE.VIM": return { "html": "

VMERGE.VIM vs2, simm5, vd

The vmerge instructions are encoded as masked instructions (vm=0). The instructions combine two sources as follows. At elements where the mask value is zero, the first operand is copied to the destination element, otherwise the second operand is copied to the destination element. The first operand is always a vector register group specified by vs2. The second operand is a vector register group specified by vs1 or a scalar x register specified by rs1 or a 5-bit sign-extended immediate.
vmerge.vvm vd, vs2, vs1, v0 # vd[i] = v0.mask[i] ? vs1[i] : vs2[i] vmerge.vxm vd, vs2, rs1, v0 # vd[i] = v0.mask[i] ? x[rs1] : vs2[i] vmerge.vim vd, vs2, imm, v0 # vd[i] = v0.mask[i] ? imm : vs2[i]

ISA: v

", "tooltip": "The vmerge instructions are encoded as masked instructions (vm=0). The instructions combine two sources as follows. At elements where the mask value is zero, the first operand is copied to the destination element, otherwise the second operand is copied to the destination element. The first operand is always a vector register group specified by vs2. The second operand is a vector register group specified by vs1 or a scalar x register specified by rs1 or a 5-bit sign-extended immediate.\nvmerge.vvm vd, vs2, vs1, v0 # vd[i] = v0.mask[i] ? vs1[i] : vs2[i] vmerge.vxm vd, vs2, rs1, v0 # vd[i] = v0.mask[i] ? x[rs1] : vs2[i] vmerge.vim vd, vs2, imm, v0 # vd[i] = v0.mask[i] ? imm : vs2[i]\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_integer_merge_instructions" }; case "VMERGE.VVM": return { "html": "

VMERGE.VVM vs2, vs1, vd

The vmerge instructions are encoded as masked instructions (vm=0). The instructions combine two sources as follows. At elements where the mask value is zero, the first operand is copied to the destination element, otherwise the second operand is copied to the destination element. The first operand is always a vector register group specified by vs2. The second operand is a vector register group specified by vs1 or a scalar x register specified by rs1 or a 5-bit sign-extended immediate.
vmerge.vvm vd, vs2, vs1, v0 # vd[i] = v0.mask[i] ? vs1[i] : vs2[i] vmerge.vxm vd, vs2, rs1, v0 # vd[i] = v0.mask[i] ? x[rs1] : vs2[i] vmerge.vim vd, vs2, imm, v0 # vd[i] = v0.mask[i] ? imm : vs2[i]

ISA: v

VMERGE.VXM vs2, rs1, vd

The vmerge instructions are encoded as masked instructions (vm=0). The instructions combine two sources as follows. At elements where the mask value is zero, the first operand is copied to the destination element, otherwise the second operand is copied to the destination element. The first operand is always a vector register group specified by vs2. The second operand is a vector register group specified by vs1 or a scalar x register specified by rs1 or a 5-bit sign-extended immediate.
vmerge.vvm vd, vs2, vs1, v0 # vd[i] = v0.mask[i] ? vs1[i] : vs2[i] vmerge.vxm vd, vs2, rs1, v0 # vd[i] = v0.mask[i] ? x[rs1] : vs2[i] vmerge.vim vd, vs2, imm, v0 # vd[i] = v0.mask[i] ? imm : vs2[i]

ISA: v

VMFEQ.VF vs2, rs1, vd

The compare instructions follow the semantics of the scalar floating-point compare instructions. vmfeq and vmfne raise the invalid operation exception only on signaling NaN inputs. vmflt, vmfle, vmfgt, and vmfge raise the invalid operation exception on both signaling and quiet NaN inputs. vmfne writes 1 to the destination element when either operand is NaN, whereas the other compares write 0 when either operand is NaN.
# Compare equal vmfeq.vv vd, vs2, vs1, vm # Vector-vector vmfeq.vf vd, vs2, rs1, vm # vector-scalar # Compare not equal vmfne.vv vd, vs2, vs1, vm # Vector-vector vmfne.vf vd, vs2, rs1, vm # vector-scalar # Compare less than vmflt.vv vd, vs2, vs1, vm # Vector-vector vmflt.vf vd, vs2, rs1, vm # vector-scalar # Compare less than or equal vmfle.vv vd, vs2, vs1, vm # Vector-vector vmfle.vf vd, vs2, rs1, vm # vector-scalar # Compare greater than vmfgt.vf vd, vs2, rs1, vm # vector-scalar # Compare greater than or equal vmfge.vf vd, vs2, rs1, vm # vector-scalar
# Example of implementing isgreater() vmfeq.vv v0, va, va # Only set where A is not NaN. vmfeq.vv v1, vb, vb # Only set where B is not NaN. vmand.mm v0, v0, v1 # Only set where A and B are ordered, vmfgt.vv v0, va, vb, v0.t # so only set flags on ordered values.

ISA: v

", "tooltip": "The compare instructions follow the semantics of the scalar floating-point compare instructions. vmfeq and vmfne raise the invalid operation exception only on signaling NaN inputs. vmflt, vmfle, vmfgt, and vmfge raise the invalid operation exception on both signaling and quiet NaN inputs. vmfne writes 1 to the destination element when either operand is NaN, whereas the other compares write 0 when either operand is NaN.\n# Compare equal vmfeq.vv vd, vs2, vs1, vm # Vector-vector vmfeq.vf vd, vs2, rs1, vm # vector-scalar # Compare not equal vmfne.vv vd, vs2, vs1, vm # Vector-vector vmfne.vf vd, vs2, rs1, vm # vector-scalar # Compare less than vmflt.vv vd, vs2, vs1, vm # Vector-vector vmflt.vf vd, vs2, rs1, vm # vector-scalar # Compare less than or equal vmfle.vv vd, vs2, vs1, vm # Vector-vector vmfle.vf vd, vs2, rs1, vm # vector-scalar # Compare greater than vmfgt.vf vd, vs2, rs1, vm # vector-scalar # Compare greater than or equal vmfge.vf vd, vs2, rs1, vm # vector-scalar\n# Example of implementing isgreater() vmfeq.vv v0, va, va # Only set where A is not NaN. vmfeq.vv v1, vb, vb # Only set where B is not NaN. vmand.mm v0, v0, v1 # Only set where A and B are ordered, vmfgt.vv v0, va, vb, v0.t # so only set flags on ordered values.\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_floating_point_compare_instructions" }; case "VMFEQ.VV": return { "html": "

VMFEQ.VV vs2, vs1, vd

The compare instructions follow the semantics of the scalar floating-point compare instructions. vmfeq and vmfne raise the invalid operation exception only on signaling NaN inputs. vmflt, vmfle, vmfgt, and vmfge raise the invalid operation exception on both signaling and quiet NaN inputs. vmfne writes 1 to the destination element when either operand is NaN, whereas the other compares write 0 when either operand is NaN.
# Compare equal vmfeq.vv vd, vs2, vs1, vm # Vector-vector vmfeq.vf vd, vs2, rs1, vm # vector-scalar # Compare not equal vmfne.vv vd, vs2, vs1, vm # Vector-vector vmfne.vf vd, vs2, rs1, vm # vector-scalar # Compare less than vmflt.vv vd, vs2, vs1, vm # Vector-vector vmflt.vf vd, vs2, rs1, vm # vector-scalar # Compare less than or equal vmfle.vv vd, vs2, vs1, vm # Vector-vector vmfle.vf vd, vs2, rs1, vm # vector-scalar # Compare greater than vmfgt.vf vd, vs2, rs1, vm # vector-scalar # Compare greater than or equal vmfge.vf vd, vs2, rs1, vm # vector-scalar
# Example of implementing isgreater() vmfeq.vv v0, va, va # Only set where A is not NaN. vmfeq.vv v1, vb, vb # Only set where B is not NaN. vmand.mm v0, v0, v1 # Only set where A and B are ordered, vmfgt.vv v0, va, vb, v0.t # so only set flags on ordered values.

ISA: v

VMFGE.VF vs2, rs1, vd

vmfge

ISA: v

", "tooltip": "vmfge\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMFGT.VF": return { "html": "

VMFGT.VF vs2, rs1, vd

vmfgt

ISA: v

", "tooltip": "vmfgt\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMFLE.VF": return { "html": "

VMFLE.VF vs2, rs1, vd

vmfle

ISA: v

", "tooltip": "vmfle\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMFLE.VV": return { "html": "

VMFLE.VV vs2, vs1, vd

vmfle

ISA: v

", "tooltip": "vmfle\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMFLT.VF": return { "html": "

VMFLT.VF vs2, rs1, vd

Comparison Assembler Mapping Assembler pseudoinstruction va < vb vmflt.vv vd, va, vb, vm va <= vb vmfle.vv vd, va, vb, vm va > vb vmflt.vv vd, vb, va, vm vmfgt.vv vd, va, vb, vm va >= vb vmfle.vv vd, vb, va, vm vmfge.vv vd, va, vb, vm va < f vmflt.vf vd, va, f, vm va <= f vmfle.vf vd, va, f, vm va > f vmfgt.vf vd, va, f, vm va >= f vmfge.vf vd, va, f, vm va, vb vector register groups f scalar floating-point register

ISA: v

", "tooltip": "Comparison Assembler Mapping Assembler pseudoinstruction va < vb vmflt.vv vd, va, vb, vm va <= vb vmfle.vv vd, va, vb, vm va > vb vmflt.vv vd, vb, va, vm vmfgt.vv vd, va, vb, vm va >= vb vmfle.vv vd, vb, va, vm vmfge.vv vd, va, vb, vm va < f vmflt.vf vd, va, f, vm va <= f vmfle.vf vd, va, f, vm va > f vmfgt.vf vd, va, f, vm va >= f vmfge.vf vd, va, f, vm va, vb vector register groups f scalar floating-point register\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_floating_point_compare_instructions" }; case "VMFLT.VV": return { "html": "

VMFLT.VV vs2, vs1, vd

Comparison Assembler Mapping Assembler pseudoinstruction va < vb vmflt.vv vd, va, vb, vm va <= vb vmfle.vv vd, va, vb, vm va > vb vmflt.vv vd, vb, va, vm vmfgt.vv vd, va, vb, vm va >= vb vmfle.vv vd, vb, va, vm vmfge.vv vd, va, vb, vm va < f vmflt.vf vd, va, f, vm va <= f vmfle.vf vd, va, f, vm va > f vmfgt.vf vd, va, f, vm va >= f vmfge.vf vd, va, f, vm va, vb vector register groups f scalar floating-point register

ISA: v

VMFNE.VF vs2, rs1, vd

vmfne

ISA: v

", "tooltip": "vmfne\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMFNE.VV": return { "html": "

VMFNE.VV vs2, vs1, vd

vmfne

ISA: v

", "tooltip": "vmfne\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMIN.VV": return { "html": "

VMIN.VV vs2, vs1, vd

vmin

ISA: v

", "tooltip": "vmin\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMIN.VX": return { "html": "

VMIN.VX vs2, rs1, vd

vmin

ISA: v

", "tooltip": "vmin\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMINU.VV": return { "html": "

VMINU.VV vs2, vs1, vd

# Unsigned minimum vminu.vv vd, vs2, vs1, vm # Vector-vector vminu.vx vd, vs2, rs1, vm # vector-scalar # Signed minimum vmin.vv vd, vs2, vs1, vm # Vector-vector vmin.vx vd, vs2, rs1, vm # vector-scalar # Unsigned maximum vmaxu.vv vd, vs2, vs1, vm # Vector-vector vmaxu.vx vd, vs2, rs1, vm # vector-scalar # Signed maximum vmax.vv vd, vs2, vs1, vm # Vector-vector vmax.vx vd, vs2, rs1, vm # vector-scalar

ISA: v

", "tooltip": "# Unsigned minimum vminu.vv vd, vs2, vs1, vm # Vector-vector vminu.vx vd, vs2, rs1, vm # vector-scalar # Signed minimum vmin.vv vd, vs2, vs1, vm # Vector-vector vmin.vx vd, vs2, rs1, vm # vector-scalar # Unsigned maximum vmaxu.vv vd, vs2, vs1, vm # Vector-vector vmaxu.vx vd, vs2, rs1, vm # vector-scalar # Signed maximum vmax.vv vd, vs2, vs1, vm # Vector-vector vmax.vx vd, vs2, rs1, vm # vector-scalar\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_integer_minmax_instructions" }; case "VMINU.VX": return { "html": "

VMINU.VX vs2, rs1, vd

# Unsigned minimum vminu.vv vd, vs2, vs1, vm # Vector-vector vminu.vx vd, vs2, rs1, vm # vector-scalar # Signed minimum vmin.vv vd, vs2, vs1, vm # Vector-vector vmin.vx vd, vs2, rs1, vm # vector-scalar # Unsigned maximum vmaxu.vv vd, vs2, vs1, vm # Vector-vector vmaxu.vx vd, vs2, rs1, vm # vector-scalar # Signed maximum vmax.vv vd, vs2, vs1, vm # Vector-vector vmax.vx vd, vs2, rs1, vm # vector-scalar

ISA: v

VMNAND.MM vs2, vs1, vd

vmnand.mm vd, src1, src1
vmnand.mm vd, src2, src2
vmnand.mm vd, src1, src2

ISA: v

", "tooltip": "vmnand.mm vd, src1, src1\nvmnand.mm vd, src2, src2\nvmnand.mm vd, src1, src2\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#sec-mask-register-logical" }; case "VMNOR.MM": return { "html": "

VMNOR.MM vs2, vs1, vd

vmnor.mm vd, src1, src2

ISA: v

", "tooltip": "vmnor.mm vd, src1, src2\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#sec-mask-register-logical" }; case "VMOR.MM": return { "html": "

VMOR.MM vs2, vs1, vd

vmor

ISA: v

", "tooltip": "vmor\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMORN.MM": return { "html": "

VMORN.MM vs2, vs1, vd

vmorn.mm vd, src2, src1
vmorn.mm vd, src1, src2

ISA: v

", "tooltip": "vmorn.mm vd, src2, src1\nvmorn.mm vd, src1, src2\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#sec-mask-register-logical" }; case "VMORNOT.MM": return { "html": "

VMORNOT.MM vs2, vs1, vd

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VMSBC.VV": return { "html": "

VMSBC.VV vs2, vs1, vd

For vmsbc, the borrow is defined to be 1 iff the difference, prior to truncation, is negative.

ISA: v

", "tooltip": "For vmsbc, the borrow is defined to be 1 iff the difference, prior to truncation, is negative.\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_integer_add_with_carry_subtract_with_borrow_instructions" }; case "VMSBC.VVM": return { "html": "

VMSBC.VVM vs2, vs1, vd

For vmsbc, the borrow is defined to be 1 iff the difference, prior to truncation, is negative.

ISA: v

VMSBC.VX vs2, rs1, vd

For vmsbc, the borrow is defined to be 1 iff the difference, prior to truncation, is negative.

ISA: v

VMSBC.VXM vs2, rs1, vd

For vmsbc, the borrow is defined to be 1 iff the difference, prior to truncation, is negative.

ISA: v

VMSBF.M vs2, vd

In addition, except for mask load instructions, any element in the tail of a mask result can also be written with the value the mask-producing operation would have calculated with vl=VLMAX. Furthermore, for mask-logical instructions and vmsbf.m, vmsif.m, vmsof.m mask-manipulation instructions, any element in the tail of the result can be written with the value the mask-producing operation would have calculated with vl=VLEN, SEW=8, and LMUL=8 (i.e., all bits of the mask register can be overwritten).

ISA: v

", "tooltip": "In addition, except for mask load instructions, any element in the tail of a mask result can also be written with the value the mask-producing operation would have calculated with vl=VLMAX. Furthermore, for mask-logical instructions and vmsbf.m, vmsif.m, vmsof.m mask-manipulation instructions, any element in the tail of the result can be written with the value the mask-producing operation would have calculated with vl=VLEN, SEW=8, and LMUL=8 (i.e., all bits of the mask register can be overwritten).\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#sec-agnostic" }; case "VMSEQ.VI": return { "html": "

VMSEQ.VI vs2, simm5, vd

# Set if equal vmseq.vv vd, vs2, vs1, vm # Vector-vector vmseq.vx vd, vs2, rs1, vm # vector-scalar vmseq.vi vd, vs2, imm, vm # vector-immediate # Set if not equal vmsne.vv vd, vs2, vs1, vm # Vector-vector vmsne.vx vd, vs2, rs1, vm # vector-scalar vmsne.vi vd, vs2, imm, vm # vector-immediate # Set if less than, unsigned vmsltu.vv vd, vs2, vs1, vm # Vector-vector vmsltu.vx vd, vs2, rs1, vm # Vector-scalar # Set if less than, signed vmslt.vv vd, vs2, vs1, vm # Vector-vector vmslt.vx vd, vs2, rs1, vm # vector-scalar # Set if less than or equal, unsigned vmsleu.vv vd, vs2, vs1, vm # Vector-vector vmsleu.vx vd, vs2, rs1, vm # vector-scalar vmsleu.vi vd, vs2, imm, vm # Vector-immediate # Set if less than or equal, signed vmsle.vv vd, vs2, vs1, vm # Vector-vector vmsle.vx vd, vs2, rs1, vm # vector-scalar vmsle.vi vd, vs2, imm, vm # vector-immediate # Set if greater than, unsigned vmsgtu.vx vd, vs2, rs1, vm # Vector-scalar vmsgtu.vi vd, vs2, imm, vm # Vector-immediate # Set if greater than, signed vmsgt.vx vd, vs2, rs1, vm # Vector-scalar vmsgt.vi vd, vs2, imm, vm # Vector-immediate # Following two instructions are not provided directly # Set if greater than or equal, unsigned # vmsgeu.vx vd, vs2, rs1, vm # Vector-scalar # Set if greater than or equal, signed # vmsge.vx vd, vs2, rs1, vm # Vector-scalar

ISA: v

", "tooltip": "# Set if equal vmseq.vv vd, vs2, vs1, vm # Vector-vector vmseq.vx vd, vs2, rs1, vm # vector-scalar vmseq.vi vd, vs2, imm, vm # vector-immediate # Set if not equal vmsne.vv vd, vs2, vs1, vm # Vector-vector vmsne.vx vd, vs2, rs1, vm # vector-scalar vmsne.vi vd, vs2, imm, vm # vector-immediate # Set if less than, unsigned vmsltu.vv vd, vs2, vs1, vm # Vector-vector vmsltu.vx vd, vs2, rs1, vm # Vector-scalar # Set if less than, signed vmslt.vv vd, vs2, vs1, vm # Vector-vector vmslt.vx vd, vs2, rs1, vm # vector-scalar # Set if less than or equal, unsigned vmsleu.vv vd, vs2, vs1, vm # Vector-vector vmsleu.vx vd, vs2, rs1, vm # vector-scalar vmsleu.vi vd, vs2, imm, vm # Vector-immediate # Set if less than or equal, signed vmsle.vv vd, vs2, vs1, vm # Vector-vector vmsle.vx vd, vs2, rs1, vm # vector-scalar vmsle.vi vd, vs2, imm, vm # vector-immediate # Set if greater than, unsigned vmsgtu.vx vd, vs2, rs1, vm # Vector-scalar vmsgtu.vi vd, vs2, imm, vm # Vector-immediate # Set if greater than, signed vmsgt.vx vd, vs2, rs1, vm # Vector-scalar vmsgt.vi vd, vs2, imm, vm # Vector-immediate # Following two instructions are not provided directly # Set if greater than or equal, unsigned # vmsgeu.vx vd, vs2, rs1, vm # Vector-scalar # Set if greater than or equal, signed # vmsge.vx vd, vs2, rs1, vm # Vector-scalar\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_integer_compare_instructions" }; case "VMSEQ.VV": return { "html": "

VMSEQ.VV vs2, vs1, vd

# Set if equal vmseq.vv vd, vs2, vs1, vm # Vector-vector vmseq.vx vd, vs2, rs1, vm # vector-scalar vmseq.vi vd, vs2, imm, vm # vector-immediate # Set if not equal vmsne.vv vd, vs2, vs1, vm # Vector-vector vmsne.vx vd, vs2, rs1, vm # vector-scalar vmsne.vi vd, vs2, imm, vm # vector-immediate # Set if less than, unsigned vmsltu.vv vd, vs2, vs1, vm # Vector-vector vmsltu.vx vd, vs2, rs1, vm # Vector-scalar # Set if less than, signed vmslt.vv vd, vs2, vs1, vm # Vector-vector vmslt.vx vd, vs2, rs1, vm # vector-scalar # Set if less than or equal, unsigned vmsleu.vv vd, vs2, vs1, vm # Vector-vector vmsleu.vx vd, vs2, rs1, vm # vector-scalar vmsleu.vi vd, vs2, imm, vm # Vector-immediate # Set if less than or equal, signed vmsle.vv vd, vs2, vs1, vm # Vector-vector vmsle.vx vd, vs2, rs1, vm # vector-scalar vmsle.vi vd, vs2, imm, vm # vector-immediate # Set if greater than, unsigned vmsgtu.vx vd, vs2, rs1, vm # Vector-scalar vmsgtu.vi vd, vs2, imm, vm # Vector-immediate # Set if greater than, signed vmsgt.vx vd, vs2, rs1, vm # Vector-scalar vmsgt.vi vd, vs2, imm, vm # Vector-immediate # Following two instructions are not provided directly # Set if greater than or equal, unsigned # vmsgeu.vx vd, vs2, rs1, vm # Vector-scalar # Set if greater than or equal, signed # vmsge.vx vd, vs2, rs1, vm # Vector-scalar

ISA: v

VMSEQ.VX vs2, rs1, vd

# Set if equal vmseq.vv vd, vs2, vs1, vm # Vector-vector vmseq.vx vd, vs2, rs1, vm # vector-scalar vmseq.vi vd, vs2, imm, vm # vector-immediate # Set if not equal vmsne.vv vd, vs2, vs1, vm # Vector-vector vmsne.vx vd, vs2, rs1, vm # vector-scalar vmsne.vi vd, vs2, imm, vm # vector-immediate # Set if less than, unsigned vmsltu.vv vd, vs2, vs1, vm # Vector-vector vmsltu.vx vd, vs2, rs1, vm # Vector-scalar # Set if less than, signed vmslt.vv vd, vs2, vs1, vm # Vector-vector vmslt.vx vd, vs2, rs1, vm # vector-scalar # Set if less than or equal, unsigned vmsleu.vv vd, vs2, vs1, vm # Vector-vector vmsleu.vx vd, vs2, rs1, vm # vector-scalar vmsleu.vi vd, vs2, imm, vm # Vector-immediate # Set if less than or equal, signed vmsle.vv vd, vs2, vs1, vm # Vector-vector vmsle.vx vd, vs2, rs1, vm # vector-scalar vmsle.vi vd, vs2, imm, vm # vector-immediate # Set if greater than, unsigned vmsgtu.vx vd, vs2, rs1, vm # Vector-scalar vmsgtu.vi vd, vs2, imm, vm # Vector-immediate # Set if greater than, signed vmsgt.vx vd, vs2, rs1, vm # Vector-scalar vmsgt.vi vd, vs2, imm, vm # Vector-immediate # Following two instructions are not provided directly # Set if greater than or equal, unsigned # vmsgeu.vx vd, vs2, rs1, vm # Vector-scalar # Set if greater than or equal, signed # vmsge.vx vd, vs2, rs1, vm # Vector-scalar

ISA: v

VMSGT.VI vs2, simm5, vd

Similarly, vmsge{u}.vi is not provided and the compare is implemented using vmsgt{u}.vi with the immediate decremented by one. The resulting effective vmsge.vi range is -15 to 16, and the resulting effective vmsgeu.vi range is 1 to 16 (Note, vmsgeu.vi with immediate 0 is not useful as it is always true).
The vmsge{u}.vx operation can be synthesized by reducing the value of x by 1 and using the vmsgt{u}.vx instruction, when it is known that this will not underflow the representation in x.
Sequences to synthesize `vmsge{u}.vx` instruction va >= x, x > minimum addi t0, x, -1; vmsgt{u}.vx vd, va, t0, vm

ISA: v

", "tooltip": "Similarly, vmsge{u}.vi is not provided and the compare is implemented using vmsgt{u}.vi with the immediate decremented by one. The resulting effective vmsge.vi range is -15 to 16, and the resulting effective vmsgeu.vi range is 1 to 16 (Note, vmsgeu.vi with immediate 0 is not useful as it is always true).\nThe vmsge{u}.vx operation can be synthesized by reducing the value of x by 1 and using the vmsgt{u}.vx instruction, when it is known that this will not underflow the representation in x.\nSequences to synthesize `vmsge{u}.vx` instruction va >= x, x > minimum addi t0, x, -1; vmsgt{u}.vx vd, va, t0, vm\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_integer_compare_instructions" }; case "VMSGT.VX": return { "html": "

VMSGT.VX vs2, rs1, vd

ISA: v

VMSGTU.VI vs2, simm5, vd

vmsgtu

ISA: v

", "tooltip": "vmsgtu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMSGTU.VX": return { "html": "

VMSGTU.VX vs2, rs1, vd

vmsgtu

ISA: v

", "tooltip": "vmsgtu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMSIF.M": return { "html": "

VMSIF.M vs2, vd

Traps on vmsif.m are always reported with a vstart of 0. The vmsif instruction will raise an illegal instruction exception if vstart is non-zero.
vmsif.m vd, vs2, vm # Example 7 6 5 4 3 2 1 0 Element number 1 0 0 1 0 1 0 0 v3 contents vmsif.m v2, v3 0 0 0 0 0 1 1 1 v2 contents 1 0 0 1 0 1 0 1 v3 contents vmsif.m v2, v3 0 0 0 0 0 0 0 1 v2 1 1 0 0 0 0 1 1 v0 vcontents 1 0 0 1 0 1 0 0 v3 contents vmsif.m v2, v3, v0.t 1 1 x x x x 1 1 v2 contents

ISA: v

", "tooltip": "Traps on vmsif.m are always reported with a vstart of 0. The vmsif instruction will raise an illegal instruction exception if vstart is non-zero.\nvmsif.m vd, vs2, vm # Example 7 6 5 4 3 2 1 0 Element number 1 0 0 1 0 1 0 0 v3 contents vmsif.m v2, v3 0 0 0 0 0 1 1 1 v2 contents 1 0 0 1 0 1 0 1 v3 contents vmsif.m v2, v3 0 0 0 0 0 0 0 1 v2 1 1 0 0 0 0 1 1 v0 vcontents 1 0 0 1 0 1 0 0 v3 contents vmsif.m v2, v3, v0.t 1 1 x x x x 1 1 v2 contents\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vmsif_m_set_including_first_mask_bit" }; case "VMSLE.VI": return { "html": "

VMSLE.VI vs2, simm5, vd

vmsle

ISA: v

", "tooltip": "vmsle\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMSLE.VV": return { "html": "

VMSLE.VV vs2, vs1, vd

vmsle

ISA: v

", "tooltip": "vmsle\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMSLE.VX": return { "html": "

VMSLE.VX vs2, rs1, vd

vmsle

ISA: v

", "tooltip": "vmsle\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMSLEU.VI": return { "html": "

VMSLEU.VI vs2, simm5, vd

vmsleu

ISA: v

", "tooltip": "vmsleu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMSLEU.VV": return { "html": "

VMSLEU.VV vs2, vs1, vd

vmsleu

ISA: v

", "tooltip": "vmsleu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMSLEU.VX": return { "html": "

VMSLEU.VX vs2, rs1, vd

vmsleu

ISA: v

", "tooltip": "vmsleu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMSLT.VV": return { "html": "

VMSLT.VV vs2, vs1, vd

Comparison Assembler Mapping Assembler Pseudoinstruction va < vb vmslt{u}.vv vd, va, vb, vm va <= vb vmsle{u}.vv vd, va, vb, vm va > vb vmslt{u}.vv vd, vb, va, vm vmsgt{u}.vv vd, va, vb, vm va >= vb vmsle{u}.vv vd, vb, va, vm vmsge{u}.vv vd, va, vb, vm va < x vmslt{u}.vx vd, va, x, vm va <= x vmsle{u}.vx vd, va, x, vm va > x vmsgt{u}.vx vd, va, x, vm va >= x see below va < i vmsle{u}.vi vd, va, i-1, vm vmslt{u}.vi vd, va, i, vm va <= i vmsle{u}.vi vd, va, i, vm va > i vmsgt{u}.vi vd, va, i, vm va >= i vmsgt{u}.vi vd, va, i-1, vm vmsge{u}.vi vd, va, i, vm va, vb vector register groups x scalar integer register i immediate
unmasked va >= x pseudoinstruction: vmsge{u}.vx vd, va, x expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd masked va >= x, vd != v0 pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0 masked va >= x, vd == v0 pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt masked va >= x, any vd pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt expansion: vmslt{u}.vx vt, va, x; vmandn.mm vt, v0, vt; vmandn.mm vd, vd, v0; vmor.mm vd, vt, vd The vt argument to the pseudoinstruction must name a temporary vector register that is not same as vd and which will be clobbered by the pseudoinstruction
# (a < b) && (b < c) in two instructions when mask-undisturbed vmslt.vv v0, va, vb # All body elements written vmslt.vv v0, vb, vc, v0.t # Only update at set mask

ISA: v

", "tooltip": "Comparison Assembler Mapping Assembler Pseudoinstruction va < vb vmslt{u}.vv vd, va, vb, vm va <= vb vmsle{u}.vv vd, va, vb, vm va > vb vmslt{u}.vv vd, vb, va, vm vmsgt{u}.vv vd, va, vb, vm va >= vb vmsle{u}.vv vd, vb, va, vm vmsge{u}.vv vd, va, vb, vm va < x vmslt{u}.vx vd, va, x, vm va <= x vmsle{u}.vx vd, va, x, vm va > x vmsgt{u}.vx vd, va, x, vm va >= x see below va < i vmsle{u}.vi vd, va, i-1, vm vmslt{u}.vi vd, va, i, vm va <= i vmsle{u}.vi vd, va, i, vm va > i vmsgt{u}.vi vd, va, i, vm va >= i vmsgt{u}.vi vd, va, i-1, vm vmsge{u}.vi vd, va, i, vm va, vb vector register groups x scalar integer register i immediate\nunmasked va >= x pseudoinstruction: vmsge{u}.vx vd, va, x expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd masked va >= x, vd != v0 pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0 masked va >= x, vd == v0 pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt masked va >= x, any vd pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt expansion: vmslt{u}.vx vt, va, x; vmandn.mm vt, v0, vt; vmandn.mm vd, vd, v0; vmor.mm vd, vt, vd The vt argument to the pseudoinstruction must name a temporary vector register that is not same as vd and which will be clobbered by the pseudoinstruction\n# (a < b) && (b < c) in two instructions when mask-undisturbed vmslt.vv v0, va, vb # All body elements written vmslt.vv v0, vb, vc, v0.t # Only update at set mask\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_integer_compare_instructions" }; case "VMSLT.VX": return { "html": "

VMSLT.VX vs2, rs1, vd

Comparison Assembler Mapping Assembler Pseudoinstruction va < vb vmslt{u}.vv vd, va, vb, vm va <= vb vmsle{u}.vv vd, va, vb, vm va > vb vmslt{u}.vv vd, vb, va, vm vmsgt{u}.vv vd, va, vb, vm va >= vb vmsle{u}.vv vd, vb, va, vm vmsge{u}.vv vd, va, vb, vm va < x vmslt{u}.vx vd, va, x, vm va <= x vmsle{u}.vx vd, va, x, vm va > x vmsgt{u}.vx vd, va, x, vm va >= x see below va < i vmsle{u}.vi vd, va, i-1, vm vmslt{u}.vi vd, va, i, vm va <= i vmsle{u}.vi vd, va, i, vm va > i vmsgt{u}.vi vd, va, i, vm va >= i vmsgt{u}.vi vd, va, i-1, vm vmsge{u}.vi vd, va, i, vm va, vb vector register groups x scalar integer register i immediate
unmasked va >= x pseudoinstruction: vmsge{u}.vx vd, va, x expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd masked va >= x, vd != v0 pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0 masked va >= x, vd == v0 pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt masked va >= x, any vd pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt expansion: vmslt{u}.vx vt, va, x; vmandn.mm vt, v0, vt; vmandn.mm vd, vd, v0; vmor.mm vd, vt, vd The vt argument to the pseudoinstruction must name a temporary vector register that is not same as vd and which will be clobbered by the pseudoinstruction
# (a < b) && (b < c) in two instructions when mask-undisturbed vmslt.vv v0, va, vb # All body elements written vmslt.vv v0, vb, vc, v0.t # Only update at set mask

ISA: v

VMSLTU.VV vs2, vs1, vd

vmsltu

ISA: v

", "tooltip": "vmsltu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMSLTU.VX": return { "html": "

VMSLTU.VX vs2, rs1, vd

vmsltu

ISA: v

", "tooltip": "vmsltu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMSNE.VI": return { "html": "

VMSNE.VI vs2, simm5, vd

vmsne

ISA: v

", "tooltip": "vmsne\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMSNE.VV": return { "html": "

VMSNE.VV vs2, vs1, vd

vmsne

ISA: v

", "tooltip": "vmsne\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMSNE.VX": return { "html": "

VMSNE.VX vs2, rs1, vd

vmsne

ISA: v

", "tooltip": "vmsne\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMSOF.M": return { "html": "

VMSOF.M vs2, vd

Traps on vmsof.m are always reported with a vstart of 0. The vmsof instruction will raise an illegal instruction exception if vstart is non-zero.
vmsof.m vd, vs2, vm # Example 7 6 5 4 3 2 1 0 Element number 1 0 0 1 0 1 0 0 v3 contents vmsof.m v2, v3 0 0 0 0 0 1 0 0 v2 contents 1 0 0 1 0 1 0 1 v3 contents vmsof.m v2, v3 0 0 0 0 0 0 0 1 v2 1 1 0 0 0 0 1 1 v0 vcontents 1 1 0 1 0 1 0 0 v3 contents vmsof.m v2, v3, v0.t 0 1 x x x x 0 0 v2 contents

ISA: v

", "tooltip": "Traps on vmsof.m are always reported with a vstart of 0. The vmsof instruction will raise an illegal instruction exception if vstart is non-zero.\nvmsof.m vd, vs2, vm # Example 7 6 5 4 3 2 1 0 Element number 1 0 0 1 0 1 0 0 v3 contents vmsof.m v2, v3 0 0 0 0 0 1 0 0 v2 contents 1 0 0 1 0 1 0 1 v3 contents vmsof.m v2, v3 0 0 0 0 0 0 0 1 v2 1 1 0 0 0 0 1 1 v0 vcontents 1 1 0 1 0 1 0 0 v3 contents vmsof.m v2, v3, v0.t 0 1 x x x x 0 0 v2 contents\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vmsof_m_set_only_first_mask_bit" }; case "VMUL.VV": return { "html": "

VMUL.VV vs2, vs1, vd

# Signed multiply, returning low bits of product vmul.vv vd, vs2, vs1, vm # Vector-vector vmul.vx vd, vs2, rs1, vm # vector-scalar # Signed multiply, returning high bits of product vmulh.vv vd, vs2, vs1, vm # Vector-vector vmulh.vx vd, vs2, rs1, vm # vector-scalar # Unsigned multiply, returning high bits of product vmulhu.vv vd, vs2, vs1, vm # Vector-vector vmulhu.vx vd, vs2, rs1, vm # vector-scalar # Signed(vs2)-Unsigned multiply, returning high bits of product vmulhsu.vv vd, vs2, vs1, vm # Vector-vector vmulhsu.vx vd, vs2, rs1, vm # vector-scalar

ISA: v

", "tooltip": "# Signed multiply, returning low bits of product vmul.vv vd, vs2, vs1, vm # Vector-vector vmul.vx vd, vs2, rs1, vm # vector-scalar # Signed multiply, returning high bits of product vmulh.vv vd, vs2, vs1, vm # Vector-vector vmulh.vx vd, vs2, rs1, vm # vector-scalar # Unsigned multiply, returning high bits of product vmulhu.vv vd, vs2, vs1, vm # Vector-vector vmulhu.vx vd, vs2, rs1, vm # vector-scalar # Signed(vs2)-Unsigned multiply, returning high bits of product vmulhsu.vv vd, vs2, vs1, vm # Vector-vector vmulhsu.vx vd, vs2, rs1, vm # vector-scalar\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_single_width_integer_multiply_instructions" }; case "VMUL.VX": return { "html": "

VMUL.VX vs2, rs1, vd

# Signed multiply, returning low bits of product vmul.vv vd, vs2, vs1, vm # Vector-vector vmul.vx vd, vs2, rs1, vm # vector-scalar # Signed multiply, returning high bits of product vmulh.vv vd, vs2, vs1, vm # Vector-vector vmulh.vx vd, vs2, rs1, vm # vector-scalar # Unsigned multiply, returning high bits of product vmulhu.vv vd, vs2, vs1, vm # Vector-vector vmulhu.vx vd, vs2, rs1, vm # vector-scalar # Signed(vs2)-Unsigned multiply, returning high bits of product vmulhsu.vv vd, vs2, vs1, vm # Vector-vector vmulhsu.vx vd, vs2, rs1, vm # vector-scalar

ISA: v

VMULH.VV vs2, vs1, vd

All Zve* extensions support all vector integer instructions (Section Vector Integer Arithmetic Instructions ), except that the vmulh integer multiply variants that return the high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*.

ISA: v

", "tooltip": "All Zve* extensions support all vector integer instructions (Section Vector Integer Arithmetic Instructions ), except that the vmulh integer multiply variants that return the high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*.\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_zve_vector_extensions_for_embedded_processors" }; case "VMULH.VX": return { "html": "

VMULH.VX vs2, rs1, vd

All Zve* extensions support all vector integer instructions (Section Vector Integer Arithmetic Instructions ), except that the vmulh integer multiply variants that return the high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*.

ISA: v

VMULHSU.VV vs2, vs1, vd

vmulhsu

ISA: v

", "tooltip": "vmulhsu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMULHSU.VX": return { "html": "

VMULHSU.VX vs2, rs1, vd

vmulhsu

ISA: v

", "tooltip": "vmulhsu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMULHU.VV": return { "html": "

VMULHU.VV vs2, vs1, vd

vmulhu

ISA: v

", "tooltip": "vmulhu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMULHU.VX": return { "html": "

VMULHU.VX vs2, rs1, vd

vmulhu

ISA: v

", "tooltip": "vmulhu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VMV.S.X": return { "html": "

VMV.S.X rs1, vd

The vector integer move instructions copy a source operand to a vector register group. The vmv.v.v variant copies a vector register group, whereas the vmv.v.x and vmv.v.i variants splat a scalar register or immediate to all active elements of the destination vector register group. These instructions are encoded as unmasked instructions (vm=1). The first operand specifier (vs2) must contain v0, and any other vector register number in vs2 is reserved.
The form vmv.v.v vd, vd, which leaves body elements unchanged, can be used to indicate that the register will next be used with an EEW equal to SEW.
vmv.v.v vd, vs1 # vd[i] = vs1[i] vmv.v.x vd, rs1 # vd[i] = x[rs1] vmv.v.i vd, imm # vd[i] = imm

ISA: v

", "tooltip": "The vector integer move instructions copy a source operand to a vector register group. The vmv.v.v variant copies a vector register group, whereas the vmv.v.x and vmv.v.i variants splat a scalar register or immediate to all active elements of the destination vector register group. These instructions are encoded as unmasked instructions (vm=1). The first operand specifier (vs2) must contain v0, and any other vector register number in vs2 is reserved.\nThe form vmv.v.v vd, vd, which leaves body elements unchanged, can be used to indicate that the register will next be used with an EEW equal to SEW.\nvmv.v.v vd, vs1 # vd[i] = vs1[i] vmv.v.x vd, rs1 # vd[i] = x[rs1] vmv.v.i vd, imm # vd[i] = imm\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_integer_move_instructions" }; case "VMV.V.I": return { "html": "

VMV.V.I simm5, vd

The vector integer move instructions copy a source operand to a vector register group. The vmv.v.v variant copies a vector register group, whereas the vmv.v.x and vmv.v.i variants splat a scalar register or immediate to all active elements of the destination vector register group. These instructions are encoded as unmasked instructions (vm=1). The first operand specifier (vs2) must contain v0, and any other vector register number in vs2 is reserved.
The form vmv.v.v vd, vd, which leaves body elements unchanged, can be used to indicate that the register will next be used with an EEW equal to SEW.
vmv.v.v vd, vs1 # vd[i] = vs1[i] vmv.v.x vd, rs1 # vd[i] = x[rs1] vmv.v.i vd, imm # vd[i] = imm

ISA: v

VMV.V.V vs1, vd

The vector integer move instructions copy a source operand to a vector register group. The vmv.v.v variant copies a vector register group, whereas the vmv.v.x and vmv.v.i variants splat a scalar register or immediate to all active elements of the destination vector register group. These instructions are encoded as unmasked instructions (vm=1). The first operand specifier (vs2) must contain v0, and any other vector register number in vs2 is reserved.
The form vmv.v.v vd, vd, which leaves body elements unchanged, can be used to indicate that the register will next be used with an EEW equal to SEW.
vmv.v.v vd, vs1 # vd[i] = vs1[i] vmv.v.x vd, rs1 # vd[i] = x[rs1] vmv.v.i vd, imm # vd[i] = imm

ISA: v

VMV.V.X rs1, vd

The vector integer move instructions copy a source operand to a vector register group. The vmv.v.v variant copies a vector register group, whereas the vmv.v.x and vmv.v.i variants splat a scalar register or immediate to all active elements of the destination vector register group. These instructions are encoded as unmasked instructions (vm=1). The first operand specifier (vs2) must contain v0, and any other vector register number in vs2 is reserved.
The form vmv.v.v vd, vd, which leaves body elements unchanged, can be used to indicate that the register will next be used with an EEW equal to SEW.
vmv.v.v vd, vs1 # vd[i] = vs1[i] vmv.v.x vd, rs1 # vd[i] = x[rs1] vmv.v.i vd, imm # vd[i] = imm

ISA: v

VMV.X.S vs2, rd

ISA: v

VMV1R.V vs2, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VMV2R.V": return { "html": "

VMV2R.V vs2, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VMV4R.V": return { "html": "

VMV4R.V vs2, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VMV8R.V": return { "html": "

VMV8R.V vs2, vd

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VMXNOR.MM": return { "html": "

VMXNOR.MM vs2, vs1, vd

vmxnor.mm vd, src1, src2
vmxnor.mm vd, vd, vd

ISA: v

", "tooltip": "vmxnor.mm vd, src1, src2\nvmxnor.mm vd, vd, vd\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#sec-mask-register-logical" }; case "VMXOR.MM": return { "html": "

VMXOR.MM vs2, vs1, vd

vmxor.mm vd, vd, vd
vmxor.mm vd, src1, src2

ISA: v

", "tooltip": "vmxor.mm vd, vd, vd\nvmxor.mm vd, src1, src2\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#sec-mask-register-logical" }; case "VNCLIP.WI": return { "html": "

VNCLIP.WI vs2, simm5, vd

The vnclip instructions are used to pack a fixed-point value into a narrower destination. The instructions support rounding, scaling, and saturation into the final destination format. The source data is in the vector register group specified by vs2. The scaling shift amount value can come from a vector register group vs1, a scalar integer register rs1, or a zero-extended 5-bit immediate. The low lg2(2*SEW) bits of the vector or scalar shift-amount value (e.g., the low 6 bits for a SEW=64-bit to SEW=32-bit narrowing operation) are used to control the right shift amount, which provides the scaling.
For vnclip, the shifted rounded source value is treated as a signed integer and saturates if the result would overflow the destination viewed as a signed integer.

ISA: v

", "tooltip": "The vnclip instructions are used to pack a fixed-point value into a narrower destination. The instructions support rounding, scaling, and saturation into the final destination format. The source data is in the vector register group specified by vs2. The scaling shift amount value can come from a vector register group vs1, a scalar integer register rs1, or a zero-extended 5-bit immediate. The low lg2(2*SEW) bits of the vector or scalar shift-amount value (e.g., the low 6 bits for a SEW=64-bit to SEW=32-bit narrowing operation) are used to control the right shift amount, which provides the scaling.\nFor vnclip, the shifted rounded source value is treated as a signed integer and saturates if the result would overflow the destination viewed as a signed integer.\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_narrowing_fixed_point_clip_instructions" }; case "VNCLIP.WV": return { "html": "

VNCLIP.WV vs2, vs1, vd

ISA: v

VNCLIP.WX vs2, rs1, vd

ISA: v

VNCLIPU.WI vs2, simm5, vd

For vnclipu/vnclip, the rounding mode is specified in the vxrm CSR. Rounding occurs around the least-significant bit of the destination and before saturation.
For vnclipu, the shifted rounded source value is treated as an unsigned integer and saturates if the result would overflow the destination viewed as an unsigned integer.
# Narrowing unsigned clip # SEW 2*SEW SEW vnclipu.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], vs1[i])) vnclipu.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], x[rs1])) vnclipu.wi vd, vs2, uimm, vm # vd[i] = clip(roundoff_unsigned(vs2[i], uimm)) # Narrowing signed clip vnclip.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i], vs1[i])) vnclip.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i], x[rs1])) vnclip.wi vd, vs2, uimm, vm # vd[i] = clip(roundoff_signed(vs2[i], uimm))

ISA: v

", "tooltip": "For vnclipu/vnclip, the rounding mode is specified in the vxrm CSR. Rounding occurs around the least-significant bit of the destination and before saturation.\nFor vnclipu, the shifted rounded source value is treated as an unsigned integer and saturates if the result would overflow the destination viewed as an unsigned integer.\n# Narrowing unsigned clip # SEW 2*SEW SEW vnclipu.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], vs1[i])) vnclipu.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], x[rs1])) vnclipu.wi vd, vs2, uimm, vm # vd[i] = clip(roundoff_unsigned(vs2[i], uimm)) # Narrowing signed clip vnclip.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i], vs1[i])) vnclip.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i], x[rs1])) vnclip.wi vd, vs2, uimm, vm # vd[i] = clip(roundoff_signed(vs2[i], uimm))\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_narrowing_fixed_point_clip_instructions" }; case "VNCLIPU.WV": return { "html": "

VNCLIPU.WV vs2, vs1, vd

For vnclipu/vnclip, the rounding mode is specified in the vxrm CSR. Rounding occurs around the least-significant bit of the destination and before saturation.
For vnclipu, the shifted rounded source value is treated as an unsigned integer and saturates if the result would overflow the destination viewed as an unsigned integer.
# Narrowing unsigned clip # SEW 2*SEW SEW vnclipu.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], vs1[i])) vnclipu.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], x[rs1])) vnclipu.wi vd, vs2, uimm, vm # vd[i] = clip(roundoff_unsigned(vs2[i], uimm)) # Narrowing signed clip vnclip.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i], vs1[i])) vnclip.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i], x[rs1])) vnclip.wi vd, vs2, uimm, vm # vd[i] = clip(roundoff_signed(vs2[i], uimm))

ISA: v

VNCLIPU.WX vs2, rs1, vd

For vnclipu/vnclip, the rounding mode is specified in the vxrm CSR. Rounding occurs around the least-significant bit of the destination and before saturation.
For vnclipu, the shifted rounded source value is treated as an unsigned integer and saturates if the result would overflow the destination viewed as an unsigned integer.
# Narrowing unsigned clip # SEW 2*SEW SEW vnclipu.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], vs1[i])) vnclipu.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], x[rs1])) vnclipu.wi vd, vs2, uimm, vm # vd[i] = clip(roundoff_unsigned(vs2[i], uimm)) # Narrowing signed clip vnclip.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i], vs1[i])) vnclip.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i], x[rs1])) vnclip.wi vd, vs2, uimm, vm # vd[i] = clip(roundoff_signed(vs2[i], uimm))

ISA: v

VNMSAC.VV vs2, vs1, vd

vnmsac

ISA: v

", "tooltip": "vnmsac\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VNMSAC.VX": return { "html": "

VNMSAC.VX vs2, rs1, vd

vnmsac

ISA: v

", "tooltip": "vnmsac\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VNMSUB.VV": return { "html": "

VNMSUB.VV vs2, vs1, vd

vnmsub

ISA: v

", "tooltip": "vnmsub\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VNMSUB.VX": return { "html": "

VNMSUB.VX vs2, rs1, vd

vnmsub

ISA: v

", "tooltip": "vnmsub\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VNSRA.WI": return { "html": "

VNSRA.WI vs2, simm5, vd

A vn* prefix on the opcode is used to distinguish these instructions in the assembler, or a vfn* prefix for narrowing floating-point opcodes. The double-width source vector register group is signified by a w in the source operand suffix (e.g., vnsra.wv)

ISA: v

", "tooltip": "A vn* prefix on the opcode is used to distinguish these instructions in the assembler, or a vfn* prefix for narrowing floating-point opcodes. The double-width source vector register group is signified by a w in the source operand suffix (e.g., vnsra.wv)\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#sec-narrowing" }; case "VNSRA.WV": return { "html": "

VNSRA.WV vs2, vs1, vd

ISA: v

VNSRA.WX vs2, rs1, vd

ISA: v

VNSRL.WI vs2, simm5, vd

The destination EEW is smaller than the source EEW and the overlap is in the lowest-numbered part of the source register group (e.g., when LMUL=1, vnsrl.wi v0, v0, 3 is legal, but a destination of v1 is not).

ISA: v

", "tooltip": "The destination EEW is smaller than the source EEW and the overlap is in the lowest-numbered part of the source register group (e.g., when LMUL=1, vnsrl.wi v0, v0, 3 is legal, but a destination of v1 is not).\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#sec-vec-operands" }; case "VNSRL.WV": return { "html": "

VNSRL.WV vs2, vs1, vd

The destination EEW is smaller than the source EEW and the overlap is in the lowest-numbered part of the source register group (e.g., when LMUL=1, vnsrl.wi v0, v0, 3 is legal, but a destination of v1 is not).

ISA: v

VNSRL.WX vs2, rs1, vd

ISA: v

VOR.VI vs2, simm5, vd

vor

ISA: v

", "tooltip": "vor\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VOR.VV": return { "html": "

VOR.VV vs2, vs1, vd

vor

ISA: v

", "tooltip": "vor\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VOR.VX": return { "html": "

VOR.VX vs2, rs1, vd

vor

ISA: v

", "tooltip": "vor\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VPOPC.M": return { "html": "

VPOPC.M vs2, rd

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VREDAND.VS": return { "html": "

VREDAND.VS vs2, vs1, vd

vredand

ISA: v

", "tooltip": "vredand\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VREDMAX.VS": return { "html": "

VREDMAX.VS vs2, vs1, vd

vredmax

ISA: v

", "tooltip": "vredmax\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VREDMAXU.VS": return { "html": "

VREDMAXU.VS vs2, vs1, vd

vredmaxu

ISA: v

", "tooltip": "vredmaxu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VREDMIN.VS": return { "html": "

VREDMIN.VS vs2, vs1, vd

vredmin

ISA: v

", "tooltip": "vredmin\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VREDMINU.VS": return { "html": "

VREDMINU.VS vs2, vs1, vd

vredminu

ISA: v

", "tooltip": "vredminu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VREDOR.VS": return { "html": "

VREDOR.VS vs2, vs1, vd

vredor

ISA: v

", "tooltip": "vredor\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VREDSUM.VS": return { "html": "

VREDSUM.VS vs2, vs1, vd

# Simple reductions, where [*] denotes all active elements: vredsum.vs vd, vs2, vs1, vm # vd[0] = sum( vs1[0] , vs2[*] ) vredmaxu.vs vd, vs2, vs1, vm # vd[0] = maxu( vs1[0] , vs2[*] ) vredmax.vs vd, vs2, vs1, vm # vd[0] = max( vs1[0] , vs2[*] ) vredminu.vs vd, vs2, vs1, vm # vd[0] = minu( vs1[0] , vs2[*] ) vredmin.vs vd, vs2, vs1, vm # vd[0] = min( vs1[0] , vs2[*] ) vredand.vs vd, vs2, vs1, vm # vd[0] = and( vs1[0] , vs2[*] ) vredor.vs vd, vs2, vs1, vm # vd[0] = or( vs1[0] , vs2[*] ) vredxor.vs vd, vs2, vs1, vm # vd[0] = xor( vs1[0] , vs2[*] )

ISA: v

", "tooltip": "# Simple reductions, where [*] denotes all active elements: vredsum.vs vd, vs2, vs1, vm # vd[0] = sum( vs1[0] , vs2[*] ) vredmaxu.vs vd, vs2, vs1, vm # vd[0] = maxu( vs1[0] , vs2[*] ) vredmax.vs vd, vs2, vs1, vm # vd[0] = max( vs1[0] , vs2[*] ) vredminu.vs vd, vs2, vs1, vm # vd[0] = minu( vs1[0] , vs2[*] ) vredmin.vs vd, vs2, vs1, vm # vd[0] = min( vs1[0] , vs2[*] ) vredand.vs vd, vs2, vs1, vm # vd[0] = and( vs1[0] , vs2[*] ) vredor.vs vd, vs2, vs1, vm # vd[0] = or( vs1[0] , vs2[*] ) vredxor.vs vd, vs2, vs1, vm # vd[0] = xor( vs1[0] , vs2[*] )\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#sec-vector-integer-reduce" }; case "VREDXOR.VS": return { "html": "

VREDXOR.VS vs2, vs1, vd

vredxor

ISA: v

", "tooltip": "vredxor\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VREM.VV": return { "html": "

VREM.VV vs2, vs1, vd

vrem

ISA: v

", "tooltip": "vrem\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VREM.VX": return { "html": "

VREM.VX vs2, rs1, vd

vrem

ISA: v

", "tooltip": "vrem\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VREMU.VV": return { "html": "

VREMU.VV vs2, vs1, vd

vremu

ISA: v

", "tooltip": "vremu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VREMU.VX": return { "html": "

VREMU.VX vs2, rs1, vd

vremu

ISA: v

", "tooltip": "vremu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VRGATHER.VI": return { "html": "

VRGATHER.VI vs2, simm5, vd

The vrgather.vv form uses SEW/LMUL for both the data and indices. The vrgatherei16.vv form uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1.
For any vrgather instruction, the destination vector register group cannot overlap with the source vector register groups, otherwise the instruction encoding is reserved.
vrgather.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; vrgatherei16.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]];
vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[x[rs1]] vrgather.vi vd, vs2, uimm, vm # vd[i] = (uimm >= VLMAX) ? 0 : vs2[uimm]

ISA: v

", "tooltip": "The vrgather.vv form uses SEW/LMUL for both the data and indices. The vrgatherei16.vv form uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1.\nFor any vrgather instruction, the destination vector register group cannot overlap with the source vector register groups, otherwise the instruction encoding is reserved.\nvrgather.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; vrgatherei16.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]];\nvrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[x[rs1]] vrgather.vi vd, vs2, uimm, vm # vd[i] = (uimm >= VLMAX) ? 0 : vs2[uimm]\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_register_gather_instructions" }; case "VRGATHER.VV": return { "html": "

VRGATHER.VV vs2, vs1, vd

The vrgather.vv form uses SEW/LMUL for both the data and indices. The vrgatherei16.vv form uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1.
For any vrgather instruction, the destination vector register group cannot overlap with the source vector register groups, otherwise the instruction encoding is reserved.
vrgather.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; vrgatherei16.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]];
vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[x[rs1]] vrgather.vi vd, vs2, uimm, vm # vd[i] = (uimm >= VLMAX) ? 0 : vs2[uimm]

ISA: v

VRGATHER.VX vs2, rs1, vd

The vrgather.vv form uses SEW/LMUL for both the data and indices. The vrgatherei16.vv form uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1.
For any vrgather instruction, the destination vector register group cannot overlap with the source vector register groups, otherwise the instruction encoding is reserved.
vrgather.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; vrgatherei16.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]];
vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[x[rs1]] vrgather.vi vd, vs2, uimm, vm # vd[i] = (uimm >= VLMAX) ? 0 : vs2[uimm]

ISA: v

VRGATHEREI16.VV vs2, vs1, vd

vrgatherei16

ISA: v

", "tooltip": "vrgatherei16\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VRSUB.VI": return { "html": "

VRSUB.VI vs2, simm5, vd

vrsub

ISA: v

", "tooltip": "vrsub\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VRSUB.VX": return { "html": "

VRSUB.VX vs2, rs1, vd

vrsub

ISA: v

", "tooltip": "vrsub\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VS1R.V": return { "html": "

VS1R.V rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VS2R.V": return { "html": "

VS2R.V rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VS4R.V": return { "html": "

VS4R.V rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VS8R.V": return { "html": "

VS8R.V rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSADD.VI": return { "html": "

VSADD.VI vs2, simm5, vd

vsadd

ISA: v

", "tooltip": "vsadd\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VSADD.VV": return { "html": "

VSADD.VV vs2, vs1, vd

vsadd

ISA: v

", "tooltip": "vsadd\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VSADD.VX": return { "html": "

VSADD.VX vs2, rs1, vd

vsadd

ISA: v

", "tooltip": "vsadd\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VSADDU.VI": return { "html": "

VSADDU.VI vs2, simm5, vd

# Saturating adds of unsigned integers. vsaddu.vv vd, vs2, vs1, vm # Vector-vector vsaddu.vx vd, vs2, rs1, vm # vector-scalar vsaddu.vi vd, vs2, imm, vm # vector-immediate # Saturating adds of signed integers. vsadd.vv vd, vs2, vs1, vm # Vector-vector vsadd.vx vd, vs2, rs1, vm # vector-scalar vsadd.vi vd, vs2, imm, vm # vector-immediate # Saturating subtract of unsigned integers. vssubu.vv vd, vs2, vs1, vm # Vector-vector vssubu.vx vd, vs2, rs1, vm # vector-scalar # Saturating subtract of signed integers. vssub.vv vd, vs2, vs1, vm # Vector-vector vssub.vx vd, vs2, rs1, vm # vector-scalar

ISA: v

", "tooltip": "# Saturating adds of unsigned integers. vsaddu.vv vd, vs2, vs1, vm # Vector-vector vsaddu.vx vd, vs2, rs1, vm # vector-scalar vsaddu.vi vd, vs2, imm, vm # vector-immediate # Saturating adds of signed integers. vsadd.vv vd, vs2, vs1, vm # Vector-vector vsadd.vx vd, vs2, rs1, vm # vector-scalar vsadd.vi vd, vs2, imm, vm # vector-immediate # Saturating subtract of unsigned integers. vssubu.vv vd, vs2, vs1, vm # Vector-vector vssubu.vx vd, vs2, rs1, vm # vector-scalar # Saturating subtract of signed integers. vssub.vv vd, vs2, vs1, vm # Vector-vector vssub.vx vd, vs2, rs1, vm # vector-scalar\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_single_width_saturating_add_and_subtract" }; case "VSADDU.VV": return { "html": "

VSADDU.VV vs2, vs1, vd

# Saturating adds of unsigned integers. vsaddu.vv vd, vs2, vs1, vm # Vector-vector vsaddu.vx vd, vs2, rs1, vm # vector-scalar vsaddu.vi vd, vs2, imm, vm # vector-immediate # Saturating adds of signed integers. vsadd.vv vd, vs2, vs1, vm # Vector-vector vsadd.vx vd, vs2, rs1, vm # vector-scalar vsadd.vi vd, vs2, imm, vm # vector-immediate # Saturating subtract of unsigned integers. vssubu.vv vd, vs2, vs1, vm # Vector-vector vssubu.vx vd, vs2, rs1, vm # vector-scalar # Saturating subtract of signed integers. vssub.vv vd, vs2, vs1, vm # Vector-vector vssub.vx vd, vs2, rs1, vm # vector-scalar

ISA: v

VSADDU.VX vs2, rs1, vd

# Saturating adds of unsigned integers. vsaddu.vv vd, vs2, vs1, vm # Vector-vector vsaddu.vx vd, vs2, rs1, vm # vector-scalar vsaddu.vi vd, vs2, imm, vm # vector-immediate # Saturating adds of signed integers. vsadd.vv vd, vs2, vs1, vm # Vector-vector vsadd.vx vd, vs2, rs1, vm # vector-scalar vsadd.vi vd, vs2, imm, vm # vector-immediate # Saturating subtract of unsigned integers. vssubu.vv vd, vs2, vs1, vm # Vector-vector vssubu.vx vd, vs2, rs1, vm # vector-scalar # Saturating subtract of signed integers. vssub.vv vd, vs2, vs1, vm # Vector-vector vssub.vx vd, vs2, rs1, vm # vector-scalar

ISA: v

VSBC.VVM vs2, vs1, vd

The subtract with borrow instruction vsbc performs the equivalent function to support long word arithmetic for subtraction. There are no subtract with immediate instructions.
# Produce difference with borrow. # vd[i] = vs2[i] - vs1[i] - v0.mask[i] vsbc.vvm vd, vs2, vs1, v0 # Vector-vector # vd[i] = vs2[i] - x[rs1] - v0.mask[i] vsbc.vxm vd, vs2, rs1, v0 # Vector-scalar # Produce borrow out in mask register format # vd.mask[i] = borrow_out(vs2[i] - vs1[i] - v0.mask[i]) vmsbc.vvm vd, vs2, vs1, v0 # Vector-vector # vd.mask[i] = borrow_out(vs2[i] - x[rs1] - v0.mask[i]) vmsbc.vxm vd, vs2, rs1, v0 # Vector-scalar # vd.mask[i] = borrow_out(vs2[i] - vs1[i]) vmsbc.vv vd, vs2, vs1 # Vector-vector, no borrow-in # vd.mask[i] = borrow_out(vs2[i] - x[rs1]) vmsbc.vx vd, vs2, rs1 # Vector-scalar, no borrow-in

ISA: v

", "tooltip": "The subtract with borrow instruction vsbc performs the equivalent function to support long word arithmetic for subtraction. There are no subtract with immediate instructions.\n# Produce difference with borrow. # vd[i] = vs2[i] - vs1[i] - v0.mask[i] vsbc.vvm vd, vs2, vs1, v0 # Vector-vector # vd[i] = vs2[i] - x[rs1] - v0.mask[i] vsbc.vxm vd, vs2, rs1, v0 # Vector-scalar # Produce borrow out in mask register format # vd.mask[i] = borrow_out(vs2[i] - vs1[i] - v0.mask[i]) vmsbc.vvm vd, vs2, vs1, v0 # Vector-vector # vd.mask[i] = borrow_out(vs2[i] - x[rs1] - v0.mask[i]) vmsbc.vxm vd, vs2, rs1, v0 # Vector-scalar # vd.mask[i] = borrow_out(vs2[i] - vs1[i]) vmsbc.vv vd, vs2, vs1 # Vector-vector, no borrow-in # vd.mask[i] = borrow_out(vs2[i] - x[rs1]) vmsbc.vx vd, vs2, rs1 # Vector-scalar, no borrow-in\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_integer_add_with_carry_subtract_with_borrow_instructions" }; case "VSBC.VXM": return { "html": "

VSBC.VXM vs2, rs1, vd

The subtract with borrow instruction vsbc performs the equivalent function to support long word arithmetic for subtraction. There are no subtract with immediate instructions.
# Produce difference with borrow. # vd[i] = vs2[i] - vs1[i] - v0.mask[i] vsbc.vvm vd, vs2, vs1, v0 # Vector-vector # vd[i] = vs2[i] - x[rs1] - v0.mask[i] vsbc.vxm vd, vs2, rs1, v0 # Vector-scalar # Produce borrow out in mask register format # vd.mask[i] = borrow_out(vs2[i] - vs1[i] - v0.mask[i]) vmsbc.vvm vd, vs2, vs1, v0 # Vector-vector # vd.mask[i] = borrow_out(vs2[i] - x[rs1] - v0.mask[i]) vmsbc.vxm vd, vs2, rs1, v0 # Vector-scalar # vd.mask[i] = borrow_out(vs2[i] - vs1[i]) vmsbc.vv vd, vs2, vs1 # Vector-vector, no borrow-in # vd.mask[i] = borrow_out(vs2[i] - x[rs1]) vmsbc.vx vd, vs2, rs1 # Vector-scalar, no borrow-in

ISA: v

VSE1.V rs1, vs3

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSE1024.V": return { "html": "

VSE1024.V rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSE128.V": return { "html": "

VSE128.V rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSE16.V": return { "html": "

VSE16.V rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSE256.V": return { "html": "

VSE256.V rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSE32.V": return { "html": "

VSE32.V rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSE512.V": return { "html": "

VSE512.V rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSE64.V": return { "html": "

VSE64.V rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSE8.V": return { "html": "

VSE8.V rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSETIVLI": return { "html": "

VSETIVLI zimm10, zimm, rd

{reg: [ {bits: 7, name: 0x57, attr: 'vsetivli'}, {bits: 5, name: 'rd', type: 4}, {bits: 3, name: 7}, {bits: 5, name: 'uimm[4:0]', type: 5}, {bits: 10, name: 'zimm[9:0]', type: 5}, {bits: 1, name: '1'}, {bits: 1, name: '1'}, ]}

ISA: v

", "tooltip": "{reg: [ {bits: 7, name: 0x57, attr: 'vsetivli'}, {bits: 5, name: 'rd', type: 4}, {bits: 3, name: 7}, {bits: 5, name: 'uimm[4:0]', type: 5}, {bits: 10, name: 'zimm[9:0]', type: 5}, {bits: 1, name: '1'}, {bits: 1, name: '1'}, ]}\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_formats" }; case "VSETVL": return { "html": "

VSETVL rs2, rs1, rd

The vector extension must have a consistent state at reset. In particular, vtype and vl must have values that can be read and then restored with a single vsetvl instruction.

ISA: v

", "tooltip": "The vector extension must have a consistent state at reset. In particular, vtype and vl must have values that can be read and then restored with a single vsetvl instruction.\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_state_of_vector_extension_at_reset" }; case "VSETVLI": return { "html": "

VSETVLI zimm11, rs1, rd

The assembly syntax adds two mandatory flags to the vsetvli instruction:
ta # Tail agnostic tu # Tail undisturbed ma # Mask agnostic mu # Mask undisturbed vsetvli t0, a0, e32, m4, ta, ma # Tail agnostic, mask agnostic vsetvli t0, a0, e32, m4, tu, ma # Tail undisturbed, mask agnostic vsetvli t0, a0, e32, m4, ta, mu # Tail agnostic, mask undisturbed vsetvli t0, a0, e32, m4, tu, mu # Tail undisturbed, mask undisturbed

ISA: v

", "tooltip": "The assembly syntax adds two mandatory flags to the vsetvli instruction:\nta # Tail agnostic tu # Tail undisturbed ma # Mask agnostic mu # Mask undisturbed vsetvli t0, a0, e32, m4, ta, ma # Tail agnostic, mask agnostic vsetvli t0, a0, e32, m4, tu, ma # Tail undisturbed, mask agnostic vsetvli t0, a0, e32, m4, ta, mu # Tail agnostic, mask undisturbed vsetvli t0, a0, e32, m4, tu, mu # Tail undisturbed, mask undisturbed\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#sec-agnostic" }; case "VSEXT.VF2": return { "html": "

VSEXT.VF2 vs2, vd

vsext.vf8
vsext.vf4
vsext.vf2

ISA: v

", "tooltip": "vsext.vf8\nvsext.vf4\nvsext.vf2\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VSEXT.VF4": return { "html": "

VSEXT.VF4 vs2, vd

vsext.vf8
vsext.vf4
vsext.vf2

ISA: v

VSEXT.VF8 vs2, vd

vsext.vf8
vsext.vf4
vsext.vf2

ISA: v

VSLIDE1DOWN.VX vs2, rs1, vd

The vslide1down instruction copies the first vl-1 active elements values from index i+1 in the source vector register group to index i in the destination vector register group.
The vslide1down instruction places the x register argument at location vl-1 in the destination vector register, provided that element vl-1 is active, otherwise the destination element is unchanged. If XLEN < SEW, the value is sign-extended to SEW bits. If XLEN > SEW, the least-significant bits are copied over and the high SEW-XLEN bits are ignored.
vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] vfslide1down.vf vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=f[rs1]
vslide1down behavior i < vstart unchanged vstart <= i < vl-1 vd[i] = vs2[i+1] if v0.mask[i] enabled vstart <= i = vl-1 vd[vl-1] = x[rs1] if v0.mask[i] enabled vl <= i < VLMAX Follow tail policy

ISA: v

", "tooltip": "The vslide1down instruction copies the first vl-1 active elements values from index i+1 in the source vector register group to index i in the destination vector register group.\nThe vslide1down instruction places the x register argument at location vl-1 in the destination vector register, provided that element vl-1 is active, otherwise the destination element is unchanged. If XLEN < SEW, the value is sign-extended to SEW bits. If XLEN > SEW, the least-significant bits are copied over and the high SEW-XLEN bits are ignored.\nvslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] vfslide1down.vf vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=f[rs1]\nvslide1down behavior i < vstart unchanged vstart <= i < vl-1 vd[i] = vs2[i+1] if v0.mask[i] enabled vstart <= i = vl-1 vd[vl-1] = x[rs1] if v0.mask[i] enabled vl <= i < VLMAX Follow tail policy\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_slide1down_instruction" }; case "VSLIDE1UP.VX": return { "html": "

VSLIDE1UP.VX vs2, rs1, vd

The vslide1up instruction places the x register argument at location 0 of the destination vector register group, provided that element 0 is active, otherwise the destination element update follows the current mask agnostic/undisturbed policy. If XLEN < SEW, the value is sign-extended to SEW bits. If XLEN > SEW, the least-significant bits are copied over and the high SEW-XLEN bits are ignored.
The vslide1up instruction requires that the destination vector register group does not overlap the source vector register group. Otherwise, the instruction encoding is reserved.
vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] vfslide1up.vf vd, vs2, rs1, vm # vd[0]=f[rs1], vd[i+1] = vs2[i]
vslide1up behavior i < vstart unchanged 0 = i = vstart vd[i] = x[rs1] if v0.mask[i] enabled max(vstart, 1) <= i < vl vd[i] = vs2[i-1] if v0.mask[i] enabled vl <= i < VLMAX Follow tail policy

ISA: v

", "tooltip": "The vslide1up instruction places the x register argument at location 0 of the destination vector register group, provided that element 0 is active, otherwise the destination element update follows the current mask agnostic/undisturbed policy. If XLEN < SEW, the value is sign-extended to SEW bits. If XLEN > SEW, the least-significant bits are copied over and the high SEW-XLEN bits are ignored.\nThe vslide1up instruction requires that the destination vector register group does not overlap the source vector register group. Otherwise, the instruction encoding is reserved.\nvslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] vfslide1up.vf vd, vs2, rs1, vm # vd[0]=f[rs1], vd[i+1] = vs2[i]\nvslide1up behavior i < vstart unchanged 0 = i = vstart vd[i] = x[rs1] if v0.mask[i] enabled max(vstart, 1) <= i < vl vd[i] = vs2[i-1] if v0.mask[i] enabled vl <= i < VLMAX Follow tail policy\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_slide1up" }; case "VSLIDEDOWN.VI": return { "html": "

VSLIDEDOWN.VI vs2, simm5, vd

For vslidedown, the value in vl specifies the maximum number of destination elements that are written. The remaining elements past vl are handled according to the current tail policy (Section Vector Tail Agnostic and Vector Mask Agnostic vta and vma ).
vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] vslidedown.vi vd, vs2, uimm, vm # vd[i] = vs2[i+uimm]
vslidedown behavior for source elements for element i in slide 0 <= i+OFFSET < VLMAX src[i] = vs2[i+OFFSET] VLMAX <= i+OFFSET src[i] = 0 vslidedown behavior for destination element i in slide 0 < i < vstart Unchanged vstart <= i < vl vd[i] = src[i] if v0.mask[i] enabled vl <= i < VLMAX Follow tail policy

ISA: v

", "tooltip": "For vslidedown, the value in vl specifies the maximum number of destination elements that are written. The remaining elements past vl are handled according to the current tail policy (Section Vector Tail Agnostic and Vector Mask Agnostic vta and vma ).\nvslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] vslidedown.vi vd, vs2, uimm, vm # vd[i] = vs2[i+uimm]\nvslidedown behavior for source elements for element i in slide 0 <= i+OFFSET < VLMAX src[i] = vs2[i+OFFSET] VLMAX <= i+OFFSET src[i] = 0 vslidedown behavior for destination element i in slide 0 < i < vstart Unchanged vstart <= i < vl vd[i] = src[i] if v0.mask[i] enabled vl <= i < VLMAX Follow tail policy\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_slidedown_instructions" }; case "VSLIDEDOWN.VX": return { "html": "

VSLIDEDOWN.VX vs2, rs1, vd

For vslidedown, the value in vl specifies the maximum number of destination elements that are written. The remaining elements past vl are handled according to the current tail policy (Section Vector Tail Agnostic and Vector Mask Agnostic vta and vma ).
vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] vslidedown.vi vd, vs2, uimm, vm # vd[i] = vs2[i+uimm]
vslidedown behavior for source elements for element i in slide 0 <= i+OFFSET < VLMAX src[i] = vs2[i+OFFSET] VLMAX <= i+OFFSET src[i] = 0 vslidedown behavior for destination element i in slide 0 < i < vstart Unchanged vstart <= i < vl vd[i] = src[i] if v0.mask[i] enabled vl <= i < VLMAX Follow tail policy

ISA: v

VSLIDEUP.VI vs2, simm5, vd

For all of the vslideup, vslidedown, v[f]slide1up, and v[f]slide1down instructions, if vstart >= vl, the instruction performs no operation and leaves the destination vector register unchanged.

ISA: v

", "tooltip": "For all of the vslideup, vslidedown, v[f]slide1up, and v[f]slide1down instructions, if vstart >= vl, the instruction performs no operation and leaves the destination vector register unchanged.\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_slide_instructions" }; case "VSLIDEUP.VX": return { "html": "

VSLIDEUP.VX vs2, rs1, vd

For all of the vslideup, vslidedown, v[f]slide1up, and v[f]slide1down instructions, if vstart >= vl, the instruction performs no operation and leaves the destination vector register unchanged.

ISA: v

VSLL.VI vs2, simm5, vd

# Bit shift operations vsll.vv vd, vs2, vs1, vm # Vector-vector vsll.vx vd, vs2, rs1, vm # vector-scalar vsll.vi vd, vs2, uimm, vm # vector-immediate vsrl.vv vd, vs2, vs1, vm # Vector-vector vsrl.vx vd, vs2, rs1, vm # vector-scalar vsrl.vi vd, vs2, uimm, vm # vector-immediate vsra.vv vd, vs2, vs1, vm # Vector-vector vsra.vx vd, vs2, rs1, vm # vector-scalar vsra.vi vd, vs2, uimm, vm # vector-immediate

ISA: v

", "tooltip": "# Bit shift operations vsll.vv vd, vs2, vs1, vm # Vector-vector vsll.vx vd, vs2, rs1, vm # vector-scalar vsll.vi vd, vs2, uimm, vm # vector-immediate vsrl.vv vd, vs2, vs1, vm # Vector-vector vsrl.vx vd, vs2, rs1, vm # vector-scalar vsrl.vi vd, vs2, uimm, vm # vector-immediate vsra.vv vd, vs2, vs1, vm # Vector-vector vsra.vx vd, vs2, rs1, vm # vector-scalar vsra.vi vd, vs2, uimm, vm # vector-immediate\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_single_width_shift_instructions" }; case "VSLL.VV": return { "html": "

VSLL.VV vs2, vs1, vd

# Bit shift operations vsll.vv vd, vs2, vs1, vm # Vector-vector vsll.vx vd, vs2, rs1, vm # vector-scalar vsll.vi vd, vs2, uimm, vm # vector-immediate vsrl.vv vd, vs2, vs1, vm # Vector-vector vsrl.vx vd, vs2, rs1, vm # vector-scalar vsrl.vi vd, vs2, uimm, vm # vector-immediate vsra.vv vd, vs2, vs1, vm # Vector-vector vsra.vx vd, vs2, rs1, vm # vector-scalar vsra.vi vd, vs2, uimm, vm # vector-immediate

ISA: v

VSLL.VX vs2, rs1, vd

# Bit shift operations vsll.vv vd, vs2, vs1, vm # Vector-vector vsll.vx vd, vs2, rs1, vm # vector-scalar vsll.vi vd, vs2, uimm, vm # vector-immediate vsrl.vv vd, vs2, vs1, vm # Vector-vector vsrl.vx vd, vs2, rs1, vm # vector-scalar vsrl.vi vd, vs2, uimm, vm # vector-immediate vsra.vv vd, vs2, vs1, vm # Vector-vector vsra.vx vd, vs2, rs1, vm # vector-scalar vsra.vi vd, vs2, uimm, vm # vector-immediate

ISA: v

VSM.V rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSMUL.VV": return { "html": "

VSMUL.VV vs2, vs1, vd

# Signed saturating and rounding fractional multiply # See vxrm description for rounding calculation vsmul.vv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i]*vs1[i], SEW-1)) vsmul.vx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i]*x[rs1], SEW-1))

ISA: v

", "tooltip": "# Signed saturating and rounding fractional multiply # See vxrm description for rounding calculation vsmul.vv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i]*vs1[i], SEW-1)) vsmul.vx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i]*x[rs1], SEW-1))\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_single_width_fractional_multiply_with_rounding_and_saturation" }; case "VSMUL.VX": return { "html": "

VSMUL.VX vs2, rs1, vd

# Signed saturating and rounding fractional multiply # See vxrm description for rounding calculation vsmul.vv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i]*vs1[i], SEW-1)) vsmul.vx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i]*x[rs1], SEW-1))

ISA: v

VSOXEI1024.V vs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSOXEI128.V": return { "html": "

VSOXEI128.V vs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSOXEI16.V": return { "html": "

VSOXEI16.V vs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSOXEI256.V": return { "html": "

VSOXEI256.V vs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSOXEI32.V": return { "html": "

VSOXEI32.V vs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSOXEI512.V": return { "html": "

VSOXEI512.V vs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSOXEI64.V": return { "html": "

VSOXEI64.V vs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSOXEI8.V": return { "html": "

VSOXEI8.V vs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSRA.VI": return { "html": "

VSRA.VI vs2, simm5, vd

vsra

ISA: v

", "tooltip": "vsra\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VSRA.VV": return { "html": "

VSRA.VV vs2, vs1, vd

vsra

ISA: v

", "tooltip": "vsra\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VSRA.VX": return { "html": "

VSRA.VX vs2, rs1, vd

vsra

ISA: v

", "tooltip": "vsra\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VSRL.VI": return { "html": "

VSRL.VI vs2, simm5, vd

vsrl

ISA: v

", "tooltip": "vsrl\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VSRL.VV": return { "html": "

VSRL.VV vs2, vs1, vd

vsrl

ISA: v

", "tooltip": "vsrl\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VSRL.VX": return { "html": "

VSRL.VX vs2, rs1, vd

vsrl

ISA: v

", "tooltip": "vsrl\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VSSE1024.V": return { "html": "

VSSE1024.V rs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSSE128.V": return { "html": "

VSSE128.V rs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSSE16.V": return { "html": "

VSSE16.V rs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSSE256.V": return { "html": "

VSSE256.V rs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSSE32.V": return { "html": "

VSSE32.V rs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSSE512.V": return { "html": "

VSSE512.V rs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSSE64.V": return { "html": "

VSSE64.V rs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSSE8.V": return { "html": "

VSSE8.V rs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSSRA.VI": return { "html": "

VSSRA.VI vs2, simm5, vd

vssra

ISA: v

", "tooltip": "vssra\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VSSRA.VV": return { "html": "

VSSRA.VV vs2, vs1, vd

vssra

ISA: v

", "tooltip": "vssra\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VSSRA.VX": return { "html": "

VSSRA.VX vs2, rs1, vd

vssra

ISA: v

", "tooltip": "vssra\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VSSRL.VI": return { "html": "

VSSRL.VI vs2, simm5, vd

These instructions shift the input value right, and round off the shifted out bits according to vxrm. The scaling right shifts have both zero-extending (vssrl) and sign-extending (vssra) forms. The data to be shifted is in the vector register group specified by vs2 and the shift amount value can come from a vector register group vs1, a scalar integer register rs1, or a zero-extended 5-bit immediate. Only the low lg2(SEW) bits of the shift-amount value are used to control the shift amount.
# Scaling shift right logical vssrl.vv vd, vs2, vs1, vm # vd[i] = roundoff_unsigned(vs2[i], vs1[i]) vssrl.vx vd, vs2, rs1, vm # vd[i] = roundoff_unsigned(vs2[i], x[rs1]) vssrl.vi vd, vs2, uimm, vm # vd[i] = roundoff_unsigned(vs2[i], uimm) # Scaling shift right arithmetic vssra.vv vd, vs2, vs1, vm # vd[i] = roundoff_signed(vs2[i],vs1[i]) vssra.vx vd, vs2, rs1, vm # vd[i] = roundoff_signed(vs2[i], x[rs1]) vssra.vi vd, vs2, uimm, vm # vd[i] = roundoff_signed(vs2[i], uimm)

ISA: v

", "tooltip": "These instructions shift the input value right, and round off the shifted out bits according to vxrm. The scaling right shifts have both zero-extending (vssrl) and sign-extending (vssra) forms. The data to be shifted is in the vector register group specified by vs2 and the shift amount value can come from a vector register group vs1, a scalar integer register rs1, or a zero-extended 5-bit immediate. Only the low lg2(SEW) bits of the shift-amount value are used to control the shift amount.\n# Scaling shift right logical vssrl.vv vd, vs2, vs1, vm # vd[i] = roundoff_unsigned(vs2[i], vs1[i]) vssrl.vx vd, vs2, rs1, vm # vd[i] = roundoff_unsigned(vs2[i], x[rs1]) vssrl.vi vd, vs2, uimm, vm # vd[i] = roundoff_unsigned(vs2[i], uimm) # Scaling shift right arithmetic vssra.vv vd, vs2, vs1, vm # vd[i] = roundoff_signed(vs2[i],vs1[i]) vssra.vx vd, vs2, rs1, vm # vd[i] = roundoff_signed(vs2[i], x[rs1]) vssra.vi vd, vs2, uimm, vm # vd[i] = roundoff_signed(vs2[i], uimm)\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_single_width_scaling_shift_instructions" }; case "VSSRL.VV": return { "html": "

VSSRL.VV vs2, vs1, vd

These instructions shift the input value right, and round off the shifted out bits according to vxrm. The scaling right shifts have both zero-extending (vssrl) and sign-extending (vssra) forms. The data to be shifted is in the vector register group specified by vs2 and the shift amount value can come from a vector register group vs1, a scalar integer register rs1, or a zero-extended 5-bit immediate. Only the low lg2(SEW) bits of the shift-amount value are used to control the shift amount.
# Scaling shift right logical vssrl.vv vd, vs2, vs1, vm # vd[i] = roundoff_unsigned(vs2[i], vs1[i]) vssrl.vx vd, vs2, rs1, vm # vd[i] = roundoff_unsigned(vs2[i], x[rs1]) vssrl.vi vd, vs2, uimm, vm # vd[i] = roundoff_unsigned(vs2[i], uimm) # Scaling shift right arithmetic vssra.vv vd, vs2, vs1, vm # vd[i] = roundoff_signed(vs2[i],vs1[i]) vssra.vx vd, vs2, rs1, vm # vd[i] = roundoff_signed(vs2[i], x[rs1]) vssra.vi vd, vs2, uimm, vm # vd[i] = roundoff_signed(vs2[i], uimm)

ISA: v

VSSRL.VX vs2, rs1, vd

These instructions shift the input value right, and round off the shifted out bits according to vxrm. The scaling right shifts have both zero-extending (vssrl) and sign-extending (vssra) forms. The data to be shifted is in the vector register group specified by vs2 and the shift amount value can come from a vector register group vs1, a scalar integer register rs1, or a zero-extended 5-bit immediate. Only the low lg2(SEW) bits of the shift-amount value are used to control the shift amount.
# Scaling shift right logical vssrl.vv vd, vs2, vs1, vm # vd[i] = roundoff_unsigned(vs2[i], vs1[i]) vssrl.vx vd, vs2, rs1, vm # vd[i] = roundoff_unsigned(vs2[i], x[rs1]) vssrl.vi vd, vs2, uimm, vm # vd[i] = roundoff_unsigned(vs2[i], uimm) # Scaling shift right arithmetic vssra.vv vd, vs2, vs1, vm # vd[i] = roundoff_signed(vs2[i],vs1[i]) vssra.vx vd, vs2, rs1, vm # vd[i] = roundoff_signed(vs2[i], x[rs1]) vssra.vi vd, vs2, uimm, vm # vd[i] = roundoff_signed(vs2[i], uimm)

ISA: v

VSSUB.VV vs2, vs1, vd

vssub

ISA: v

", "tooltip": "vssub\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VSSUB.VX": return { "html": "

VSSUB.VX vs2, rs1, vd

vssub

ISA: v

", "tooltip": "vssub\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VSSUBU.VV": return { "html": "

VSSUBU.VV vs2, vs1, vd

vssubu

ISA: v

", "tooltip": "vssubu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VSSUBU.VX": return { "html": "

VSSUBU.VX vs2, rs1, vd

vssubu

ISA: v

", "tooltip": "vssubu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VSUB.VV": return { "html": "

VSUB.VV vs2, vs1, vd

vsub

ISA: v

", "tooltip": "vsub\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VSUB.VX": return { "html": "

VSUB.VX vs2, rs1, vd

vsub

ISA: v

", "tooltip": "vsub\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VSUXEI1024.V": return { "html": "

VSUXEI1024.V vs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSUXEI128.V": return { "html": "

VSUXEI128.V vs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSUXEI16.V": return { "html": "

VSUXEI16.V vs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSUXEI256.V": return { "html": "

VSUXEI256.V vs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSUXEI32.V": return { "html": "

VSUXEI32.V vs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSUXEI512.V": return { "html": "

VSUXEI512.V vs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSUXEI64.V": return { "html": "

VSUXEI64.V vs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VSUXEI8.V": return { "html": "

VSUXEI8.V vs2, rs1, vs3

ISA: v

", "tooltip": "\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "VWADD.VV": return { "html": "

VWADD.VV vs2, vs1, vd

vwadd
vwadd.w

ISA: v

", "tooltip": "vwadd\nvwadd.w\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VWADD.VX": return { "html": "

VWADD.VX vs2, rs1, vd

vwadd
vwadd.w

ISA: v

VWADD.WV vs2, vs1, vd

vwadd
vwadd.w

ISA: v

VWADD.WX vs2, rs1, vd

vwadd
vwadd.w

ISA: v

VWADDU.VV vs2, vs1, vd

# Widening unsigned integer add/subtract, 2*SEW = SEW +/- SEW vwaddu.vv vd, vs2, vs1, vm # vector-vector vwaddu.vx vd, vs2, rs1, vm # vector-scalar vwsubu.vv vd, vs2, vs1, vm # vector-vector vwsubu.vx vd, vs2, rs1, vm # vector-scalar # Widening signed integer add/subtract, 2*SEW = SEW +/- SEW vwadd.vv vd, vs2, vs1, vm # vector-vector vwadd.vx vd, vs2, rs1, vm # vector-scalar vwsub.vv vd, vs2, vs1, vm # vector-vector vwsub.vx vd, vs2, rs1, vm # vector-scalar # Widening unsigned integer add/subtract, 2*SEW = 2*SEW +/- SEW vwaddu.wv vd, vs2, vs1, vm # vector-vector vwaddu.wx vd, vs2, rs1, vm # vector-scalar vwsubu.wv vd, vs2, vs1, vm # vector-vector vwsubu.wx vd, vs2, rs1, vm # vector-scalar # Widening signed integer add/subtract, 2*SEW = 2*SEW +/- SEW vwadd.wv vd, vs2, vs1, vm # vector-vector vwadd.wx vd, vs2, rs1, vm # vector-scalar vwsub.wv vd, vs2, vs1, vm # vector-vector vwsub.wx vd, vs2, rs1, vm # vector-scalar

ISA: v

", "tooltip": "# Widening unsigned integer add/subtract, 2*SEW = SEW +/- SEW vwaddu.vv vd, vs2, vs1, vm # vector-vector vwaddu.vx vd, vs2, rs1, vm # vector-scalar vwsubu.vv vd, vs2, vs1, vm # vector-vector vwsubu.vx vd, vs2, rs1, vm # vector-scalar # Widening signed integer add/subtract, 2*SEW = SEW +/- SEW vwadd.vv vd, vs2, vs1, vm # vector-vector vwadd.vx vd, vs2, rs1, vm # vector-scalar vwsub.vv vd, vs2, vs1, vm # vector-vector vwsub.vx vd, vs2, rs1, vm # vector-scalar # Widening unsigned integer add/subtract, 2*SEW = 2*SEW +/- SEW vwaddu.wv vd, vs2, vs1, vm # vector-vector vwaddu.wx vd, vs2, rs1, vm # vector-scalar vwsubu.wv vd, vs2, vs1, vm # vector-vector vwsubu.wx vd, vs2, rs1, vm # vector-scalar # Widening signed integer add/subtract, 2*SEW = 2*SEW +/- SEW vwadd.wv vd, vs2, vs1, vm # vector-vector vwadd.wx vd, vs2, rs1, vm # vector-scalar vwsub.wv vd, vs2, vs1, vm # vector-vector vwsub.wx vd, vs2, rs1, vm # vector-scalar\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_widening_integer_addsubtract" }; case "VWADDU.VX": return { "html": "

VWADDU.VX vs2, rs1, vd

# Widening unsigned integer add/subtract, 2*SEW = SEW +/- SEW vwaddu.vv vd, vs2, vs1, vm # vector-vector vwaddu.vx vd, vs2, rs1, vm # vector-scalar vwsubu.vv vd, vs2, vs1, vm # vector-vector vwsubu.vx vd, vs2, rs1, vm # vector-scalar # Widening signed integer add/subtract, 2*SEW = SEW +/- SEW vwadd.vv vd, vs2, vs1, vm # vector-vector vwadd.vx vd, vs2, rs1, vm # vector-scalar vwsub.vv vd, vs2, vs1, vm # vector-vector vwsub.vx vd, vs2, rs1, vm # vector-scalar # Widening unsigned integer add/subtract, 2*SEW = 2*SEW +/- SEW vwaddu.wv vd, vs2, vs1, vm # vector-vector vwaddu.wx vd, vs2, rs1, vm # vector-scalar vwsubu.wv vd, vs2, vs1, vm # vector-vector vwsubu.wx vd, vs2, rs1, vm # vector-scalar # Widening signed integer add/subtract, 2*SEW = 2*SEW +/- SEW vwadd.wv vd, vs2, vs1, vm # vector-vector vwadd.wx vd, vs2, rs1, vm # vector-scalar vwsub.wv vd, vs2, vs1, vm # vector-vector vwsub.wx vd, vs2, rs1, vm # vector-scalar

ISA: v

VWADDU.WV vs2, vs1, vd

# Widening unsigned integer add/subtract, 2*SEW = SEW +/- SEW vwaddu.vv vd, vs2, vs1, vm # vector-vector vwaddu.vx vd, vs2, rs1, vm # vector-scalar vwsubu.vv vd, vs2, vs1, vm # vector-vector vwsubu.vx vd, vs2, rs1, vm # vector-scalar # Widening signed integer add/subtract, 2*SEW = SEW +/- SEW vwadd.vv vd, vs2, vs1, vm # vector-vector vwadd.vx vd, vs2, rs1, vm # vector-scalar vwsub.vv vd, vs2, vs1, vm # vector-vector vwsub.vx vd, vs2, rs1, vm # vector-scalar # Widening unsigned integer add/subtract, 2*SEW = 2*SEW +/- SEW vwaddu.wv vd, vs2, vs1, vm # vector-vector vwaddu.wx vd, vs2, rs1, vm # vector-scalar vwsubu.wv vd, vs2, vs1, vm # vector-vector vwsubu.wx vd, vs2, rs1, vm # vector-scalar # Widening signed integer add/subtract, 2*SEW = 2*SEW +/- SEW vwadd.wv vd, vs2, vs1, vm # vector-vector vwadd.wx vd, vs2, rs1, vm # vector-scalar vwsub.wv vd, vs2, vs1, vm # vector-vector vwsub.wx vd, vs2, rs1, vm # vector-scalar

ISA: v

VWADDU.WX vs2, rs1, vd

# Widening unsigned integer add/subtract, 2*SEW = SEW +/- SEW vwaddu.vv vd, vs2, vs1, vm # vector-vector vwaddu.vx vd, vs2, rs1, vm # vector-scalar vwsubu.vv vd, vs2, vs1, vm # vector-vector vwsubu.vx vd, vs2, rs1, vm # vector-scalar # Widening signed integer add/subtract, 2*SEW = SEW +/- SEW vwadd.vv vd, vs2, vs1, vm # vector-vector vwadd.vx vd, vs2, rs1, vm # vector-scalar vwsub.vv vd, vs2, vs1, vm # vector-vector vwsub.vx vd, vs2, rs1, vm # vector-scalar # Widening unsigned integer add/subtract, 2*SEW = 2*SEW +/- SEW vwaddu.wv vd, vs2, vs1, vm # vector-vector vwaddu.wx vd, vs2, rs1, vm # vector-scalar vwsubu.wv vd, vs2, vs1, vm # vector-vector vwsubu.wx vd, vs2, rs1, vm # vector-scalar # Widening signed integer add/subtract, 2*SEW = 2*SEW +/- SEW vwadd.wv vd, vs2, vs1, vm # vector-vector vwadd.wx vd, vs2, rs1, vm # vector-scalar vwsub.wv vd, vs2, vs1, vm # vector-vector vwsub.wx vd, vs2, rs1, vm # vector-scalar

ISA: v

VWMACC.VV vs2, vs1, vd

vwmacc

ISA: v

", "tooltip": "vwmacc\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VWMACC.VX": return { "html": "

VWMACC.VX vs2, rs1, vd

vwmacc

ISA: v

", "tooltip": "vwmacc\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VWMACCSU.VV": return { "html": "

VWMACCSU.VV vs2, vs1, vd

vwmaccsu

ISA: v

", "tooltip": "vwmaccsu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VWMACCSU.VX": return { "html": "

VWMACCSU.VX vs2, rs1, vd

vwmaccsu

ISA: v

", "tooltip": "vwmaccsu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VWMACCU.VV": return { "html": "

VWMACCU.VV vs2, vs1, vd

# Widening unsigned-integer multiply-add, overwrite addend vwmaccu.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vwmaccu.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] # Widening signed-integer multiply-add, overwrite addend vwmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vwmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] # Widening signed-unsigned-integer multiply-add, overwrite addend vwmaccsu.vv vd, vs1, vs2, vm # vd[i] = +(signed(vs1[i]) * unsigned(vs2[i])) + vd[i] vwmaccsu.vx vd, rs1, vs2, vm # vd[i] = +(signed(x[rs1]) * unsigned(vs2[i])) + vd[i] # Widening unsigned-signed-integer multiply-add, overwrite addend vwmaccus.vx vd, rs1, vs2, vm # vd[i] = +(unsigned(x[rs1]) * signed(vs2[i])) + vd[i]

ISA: v

", "tooltip": "# Widening unsigned-integer multiply-add, overwrite addend vwmaccu.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vwmaccu.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] # Widening signed-integer multiply-add, overwrite addend vwmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vwmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] # Widening signed-unsigned-integer multiply-add, overwrite addend vwmaccsu.vv vd, vs1, vs2, vm # vd[i] = +(signed(vs1[i]) * unsigned(vs2[i])) + vd[i] vwmaccsu.vx vd, rs1, vs2, vm # vd[i] = +(signed(x[rs1]) * unsigned(vs2[i])) + vd[i] # Widening unsigned-signed-integer multiply-add, overwrite addend vwmaccus.vx vd, rs1, vs2, vm # vd[i] = +(unsigned(x[rs1]) * signed(vs2[i])) + vd[i]\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_widening_integer_multiply_add_instructions" }; case "VWMACCU.VX": return { "html": "

VWMACCU.VX vs2, rs1, vd

# Widening unsigned-integer multiply-add, overwrite addend vwmaccu.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vwmaccu.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] # Widening signed-integer multiply-add, overwrite addend vwmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vwmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] # Widening signed-unsigned-integer multiply-add, overwrite addend vwmaccsu.vv vd, vs1, vs2, vm # vd[i] = +(signed(vs1[i]) * unsigned(vs2[i])) + vd[i] vwmaccsu.vx vd, rs1, vs2, vm # vd[i] = +(signed(x[rs1]) * unsigned(vs2[i])) + vd[i] # Widening unsigned-signed-integer multiply-add, overwrite addend vwmaccus.vx vd, rs1, vs2, vm # vd[i] = +(unsigned(x[rs1]) * signed(vs2[i])) + vd[i]

ISA: v

VWMACCUS.VX vs2, rs1, vd

vwmaccus

ISA: v

", "tooltip": "vwmaccus\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VWMUL.VV": return { "html": "

VWMUL.VV vs2, vs1, vd

# Widening signed-integer multiply vwmul.vv vd, vs2, vs1, vm # vector-vector vwmul.vx vd, vs2, rs1, vm # vector-scalar # Widening unsigned-integer multiply vwmulu.vv vd, vs2, vs1, vm # vector-vector vwmulu.vx vd, vs2, rs1, vm # vector-scalar # Widening signed(vs2)-unsigned integer multiply vwmulsu.vv vd, vs2, vs1, vm # vector-vector vwmulsu.vx vd, vs2, rs1, vm # vector-scalar

ISA: v

", "tooltip": "# Widening signed-integer multiply vwmul.vv vd, vs2, vs1, vm # vector-vector vwmul.vx vd, vs2, rs1, vm # vector-scalar # Widening unsigned-integer multiply vwmulu.vv vd, vs2, vs1, vm # vector-vector vwmulu.vx vd, vs2, rs1, vm # vector-scalar # Widening signed(vs2)-unsigned integer multiply vwmulsu.vv vd, vs2, vs1, vm # vector-vector vwmulsu.vx vd, vs2, rs1, vm # vector-scalar\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_widening_integer_multiply_instructions" }; case "VWMUL.VX": return { "html": "

VWMUL.VX vs2, rs1, vd

# Widening signed-integer multiply vwmul.vv vd, vs2, vs1, vm # vector-vector vwmul.vx vd, vs2, rs1, vm # vector-scalar # Widening unsigned-integer multiply vwmulu.vv vd, vs2, vs1, vm # vector-vector vwmulu.vx vd, vs2, rs1, vm # vector-scalar # Widening signed(vs2)-unsigned integer multiply vwmulsu.vv vd, vs2, vs1, vm # vector-vector vwmulsu.vx vd, vs2, rs1, vm # vector-scalar

ISA: v

VWMULSU.VV vs2, vs1, vd

vwmulsu

ISA: v

", "tooltip": "vwmulsu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VWMULSU.VX": return { "html": "

VWMULSU.VX vs2, rs1, vd

vwmulsu

ISA: v

", "tooltip": "vwmulsu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VWMULU.VV": return { "html": "

VWMULU.VV vs2, vs1, vd

vwmulu

ISA: v

", "tooltip": "vwmulu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VWMULU.VX": return { "html": "

VWMULU.VX vs2, rs1, vd

vwmulu

ISA: v

", "tooltip": "vwmulu\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VWREDSUM.VS": return { "html": "

VWREDSUM.VS vs2, vs1, vd

The vwredsum.vs instruction sign-extends the SEW-wide vector elements before summing them.

ISA: v

", "tooltip": "The vwredsum.vs instruction sign-extends the SEW-wide vector elements before summing them.\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#sec-vector-integer-reduce-widen" }; case "VWREDSUMU.VS": return { "html": "

VWREDSUMU.VS vs2, vs1, vd

The unsigned vwredsumu.vs instruction zero-extends the SEW-wide vector elements before summing them, then adds the 2*SEW-width scalar element, and stores the result in a 2*SEW-width scalar element.
For both vwredsumu.vs and vwredsum.vs, overflows wrap around.
# Unsigned sum reduction into double-width accumulator vwredsumu.vs vd, vs2, vs1, vm # 2*SEW = 2*SEW + sum(zero-extend(SEW)) # Signed sum reduction into double-width accumulator vwredsum.vs vd, vs2, vs1, vm # 2*SEW = 2*SEW + sum(sign-extend(SEW))

ISA: v

", "tooltip": "The unsigned vwredsumu.vs instruction zero-extends the SEW-wide vector elements before summing them, then adds the 2*SEW-width scalar element, and stores the result in a 2*SEW-width scalar element.\nFor both vwredsumu.vs and vwredsum.vs, overflows wrap around.\n# Unsigned sum reduction into double-width accumulator vwredsumu.vs vd, vs2, vs1, vm # 2*SEW = 2*SEW + sum(zero-extend(SEW)) # Signed sum reduction into double-width accumulator vwredsum.vs vd, vs2, vs1, vm # 2*SEW = 2*SEW + sum(sign-extend(SEW))\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#sec-vector-integer-reduce-widen" }; case "VWSUB.VV": return { "html": "

VWSUB.VV vs2, vs1, vd

vwsub
vwsub.w

ISA: v

", "tooltip": "vwsub\nvwsub.w\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VWSUB.VX": return { "html": "

VWSUB.VX vs2, rs1, vd

vwsub
vwsub.w

ISA: v

VWSUB.WV vs2, vs1, vd

vwsub
vwsub.w

ISA: v

VWSUB.WX vs2, rs1, vd

vwsub
vwsub.w

ISA: v

VWSUBU.VV vs2, vs1, vd

vwsubu
vwsubu.w

ISA: v

", "tooltip": "vwsubu\nvwsubu.w\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VWSUBU.VX": return { "html": "

VWSUBU.VX vs2, rs1, vd

vwsubu
vwsubu.w

ISA: v

VWSUBU.WV vs2, vs1, vd

vwsubu
vwsubu.w

ISA: v

VWSUBU.WX vs2, rs1, vd

vwsubu
vwsubu.w

ISA: v

VXOR.VI vs2, simm5, vd

vxor

ISA: v

", "tooltip": "vxor\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VXOR.VV": return { "html": "

VXOR.VV vs2, vs1, vd

vxor

ISA: v

", "tooltip": "vxor\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VXOR.VX": return { "html": "

VXOR.VX vs2, rs1, vd

vxor

ISA: v

", "tooltip": "vxor\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#_vector_instruction_listing" }; case "VZEXT.VF2": return { "html": "

VZEXT.VF2 vs2, vd

The destination EEW is greater than the source EEW, the source EMUL is at least 1, and the overlap is in the highest-numbered part of the destination register group (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or v4 is not).

ISA: v

", "tooltip": "The destination EEW is greater than the source EEW, the source EMUL is at least 1, and the overlap is in the highest-numbered part of the destination register group (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or v4 is not).\n\n\n\n(ISA: v)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-v-spec/v1.0//v-spec.html#sec-vec-operands" }; case "VZEXT.VF4": return { "html": "

VZEXT.VF4 vs2, vd

The destination EEW is greater than the source EEW, the source EMUL is at least 1, and the overlap is in the highest-numbered part of the destination register group (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or v4 is not).

ISA: v

VZEXT.VF8 vs2, vd

ISA: v

WFI

field that supports intercepting the WFI instruction (see Section 1.3.3 ). When TW=0, the WFI instruction may execute in lower privilege modes when not prevented for some other reason. When TW=1, then if WFI is executed in any less-privileged mode, and it does not complete within an implementation-specific, bounded time limit, the WFI instruction causes an illegal instruction exception. The time limit may always be 0, in which case WFI always causes an illegal instruction exception in less-privileged modes when TW=1. TW is read-only 0 when there are no modes less privileged than M.
Trapping the WFI instruction can trigger a world switch to another guest OS, rather than wastefully idling in the current guest.
When S-mode is implemented, then executing WFI in U-mode causes an illegal instruction exception, unless it completes within an implementation-specific, bounded time limit. A future revision of this specification might add a feature that allows S-mode to selectively permit WFI in U-mode. Such a feature would only be active when TW=0.

ISA: machine

", "tooltip": "field that supports intercepting the WFI instruction (see Section 1.3.3 ). When TW=0, the WFI instruction may execute in lower privilege modes when not prevented for some other reason. When TW=1, then if WFI is executed in any less-privileged mode, and it does not complete within an implementation-specific, bounded time limit, the WFI instruction causes an illegal instruction exception. The time limit may always be 0, in which case WFI always causes an illegal instruction exception in less-privileged modes when TW=1. TW is read-only 0 when there are no modes less privileged than M.\nTrapping the WFI instruction can trigger a world switch to another guest OS, rather than wastefully idling in the current guest.\nWhen S-mode is implemented, then executing WFI in U-mode causes an illegal instruction exception, unless it completes within an implementation-specific, bounded time limit. A future revision of this specification might add a feature that allows S-mode to selectively permit WFI in U-mode. Such a feature would only be active when TW=0.\n\n\n\n(ISA: machine)", "url": "https://five-embeddev.github.io/riscv-docs-html//riscv-priv-isa-manual/Priv-v1.12/machine.html#virt-control" }; case "WRS.NTO": return { "html": "

WRS.NTO

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "WRS.STO": return { "html": "

WRS.STO

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "XNOR": return { "html": "

XNOR rd, rs1, rs2

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "XOR": return { "html": "

XOR rd, rs1, rs2

ISA: rv32

XORI rd, rs1, imm12

ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs a bitwise logical inversion of register rs1 (assembler pseudoinstruction NOT rd, rs).

ISA: rv32

ZEXT.B rd, rs

Equivalent ASM:

andi rd, rs, 255

ISA: (pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\nandi rd, rs, 255\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "ZEXT.H": return { "html": "

ZEXT.H rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "ZEXT.W": return { "html": "

ZEXT.W rd, rs

Equivalent ASM:

slli rd, rs, XLEN - 32\nsrli rd, rd, XLEN - 32

ISA: (pseudo)

", "tooltip": "Psuedo Instruction.\n\nEquivalent ASM:\n\nslli rd, rs, XLEN - 32\nsrli rd, rd, XLEN - 32\n\n", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; case "ZIP": return { "html": "

ZIP rd, rs1

ISA:

", "tooltip": "\n\n(ISA: )", "url": "https://five-embeddev.github.io/riscv-docs-html/" }; } }